Struct GenericPcieRootComplexBuilder 

pub struct GenericPcieRootComplexBuilder<'a> { /* private fields */ }

Builder for GenericPcieRootComplex.

Obtain via GenericPcieRootComplex::builder, configure optional settings, then call build.

Implementations

impl<'a> GenericPcieRootComplexBuilder<'a>

pub fn root_ports( self, ports: Vec<GenericPcieRootPortDefinition>, msi_target: &'a MsiTarget, ) -> Self

Add root ports to the complex.

msi_target is the MSI target for all root ports; the caller is responsible for creating the MsiConnection and connecting it to the platform’s interrupt controller.

pub fn first_port_device_number(self, device: u8) -> Self

Set the first PCI device number to assign to root ports (default 0).

Root ports are placed at consecutive device numbers starting from this value. Use a non-zero value to reserve lower device numbers for RCiEPs (e.g., an IOMMU at device 0).

pub fn chbcr_range(self, range: Option<MemoryRange>) -> Self

Set the CHBCR (Component Register BAR) MMIO range for CXL mode.

When set, CXL component registers are allocated and a CHBCR MMIO region is mapped.

pub fn build(self) -> Result<GenericPcieRootComplex, InvalidRootComplexError>

Build the root complex.

Returns an error if the root port count exceeds the available device/function slots (32 devices × 8 functions = 256 max).