Struct PcieHostBridge 

pub struct PcieHostBridge {
    pub index: u32,
    pub segment: u16,
    pub start_bus: u8,
    pub end_bus: u8,
    pub ecam_range: MemoryRange,
    pub low_mmio: MemoryRange,
    pub high_mmio: MemoryRange,
    pub cxl: Option<PcieHostBridgeCxlInfo>,
    pub vnode: Option<u32>,
    pub preserve_bars: bool,
    pub preserve_boot_config: bool,
}

A description of a PCI Express Root Complex, as visible to the CPU.

Fields

index: u32

A unique integer index of this host bridge in the VM.

segment: u16

PCIe segment number.

start_bus: u8

Lowest valid bus number.

end_bus: u8

Highest valid bus number.

ecam_range: MemoryRange

Memory range used for configuration space access.

low_mmio: MemoryRange

Memory range used for low MMIO.

high_mmio: MemoryRange

Memory range used for high MMIO.

cxl: Option<PcieHostBridgeCxlInfo>

CXL metadata when this host bridge supports CXL.

vnode: Option<u32>

NUMA node affinity for this host bridge.

preserve_bars: bool

When true, treat non-zero BAR values found during probing as pinned addresses (input to the PCI resource assignment algorithm). Used for P2P DMA with GPA = HPA.

preserve_boot_config: bool

When true, instruct the guest OS — via the host-bridge _DSM (and the device-tree equivalent on ARM64) — to preserve the firmware-assigned PCI boot configuration (bus numbers and BARs) rather than re-enumerating. Required when something references a device by a fixed BDF, e.g. an SRAT generic-initiator entry.