vm_topology/
pcie.rs

1// Copyright (c) Microsoft Corporation.
2// Licensed under the MIT License.
3
4//! PCI Express topology types.
5
6use crate::cxl::CfmwsWindowRestrictions;
7use memory_range::MemoryRange;
8
9/// CXL-specific host bridge metadata.
10pub struct PcieHostBridgeCxlInfo {
11    /// Memory range reserved for the CHBCR aperture.
12    pub chbcr_range: MemoryRange,
13    /// Memory range reserved for the HDM decoder.
14    pub hdm_range: MemoryRange,
15    /// CFMWS HDM window restrictions.
16    pub hdm_window_restrictions: CfmwsWindowRestrictions,
17}
18
19/// A description of a PCI Express Root Complex, as visible to the CPU.
20pub struct PcieHostBridge {
21    /// A unique integer index of this host bridge in the VM.
22    pub index: u32,
23    /// PCIe segment number.
24    pub segment: u16,
25    /// Lowest valid bus number.
26    pub start_bus: u8,
27    /// Highest valid bus number.
28    pub end_bus: u8,
29    /// Memory range used for configuration space access.
30    pub ecam_range: MemoryRange,
31    /// Memory range used for low MMIO.
32    pub low_mmio: MemoryRange,
33    /// Memory range used for high MMIO.
34    pub high_mmio: MemoryRange,
35    /// CXL metadata when this host bridge supports CXL.
36    pub cxl: Option<PcieHostBridgeCxlInfo>,
37    /// NUMA node affinity for this host bridge.
38    pub vnode: Option<u32>,
39    /// When true, treat non-zero BAR values found during probing as pinned
40    /// addresses (input to the PCI resource assignment algorithm). Used for
41    /// P2P DMA with GPA = HPA.
42    pub preserve_bars: bool,
43    /// When true, instruct the guest OS — via the host-bridge `_DSM` (and the
44    /// device-tree equivalent on ARM64) — to preserve the firmware-assigned
45    /// PCI boot configuration (bus numbers and BARs) rather than
46    /// re-enumerating. Required when something references a device by a fixed
47    /// BDF, e.g. an SRAT generic-initiator entry.
48    pub preserve_boot_config: bool,
49}
vm_topology/pcie.rs

vm_topology/
pcie.rs
