Expand description
MMIO register definitions for the Intel VT-d IOMMU.
Based on the Intel VT-d Specification Rev 4.1, §10.4 (Register Descriptions). VT-d is a pure MMIO device — no PCI config space.
Structs§
- CapReg
- Capability Register (MMIO offset 0x008, 64-bit, RO). §10.4.2.
- CcmdReg
- Context Command Register (MMIO offset 0x028, 64-bit, RW). §10.4.7.
- EcapReg
- Extended Capability Register (MMIO offset 0x010, 64-bit, RO). §11.4.3.
- Fault
Reason - VT-d fault reason codes.
- Feaddr
Reg - Fault Event Address Register (MMIO offset 0x040, 32-bit, RW). §10.4.12.
- Fectl
Reg - Fault Event Control Register (MMIO offset 0x038, 32-bit, RW). §10.4.10.
- Fedata
Reg - Fault Event Data Register (MMIO offset 0x03C, 32-bit, RW). §10.4.11.
- FrcdHi
- Fault Recording Register — high 64 bits (CAP.FRO*16 + 8). §11.4.7.6.
- FrcdLo
- Fault Recording Register — low 64 bits (CAP.FRO*16). §11.4.7.6.
- FstsReg
- Fault Status Register (MMIO offset 0x034, 32-bit, RW1C). §10.4.9.
- GcmdReg
- Global Command Register (MMIO offset 0x018, 32-bit, WO). §10.4.4.
- GstsReg
- Global Status Register (MMIO offset 0x01C, 32-bit, RO). §10.4.5.
- IcsReg
- Invalidation Completion Status Register (MMIO offset 0x09C, 32-bit, RW1C). §10.4.20.
- Iectl
Reg - Invalidation Event Control Register (MMIO offset 0x0A0, 32-bit, RW). §10.4.21.
- Iotlb
Reg - IOTLB Invalidate Register (ECAP.IRO*16 + 0x08, 64-bit, RW). §10.4.16.
- IqaReg
- Invalidation Queue Address Register (MMIO offset 0x090, 64-bit, RW). §11.4.9.3.
- IqhReg
- Invalidation Queue Head Register (MMIO offset 0x080, 64-bit). §10.4.17.
- IqtReg
- Invalidation Queue Tail Register (MMIO offset 0x088, 64-bit, RW). §10.4.18.
- IrtaReg
- Interrupt Remapping Table Address Register (MMIO offset 0x0B8, 64-bit, RW). §10.4.29.
- Mmio
Register - MMIO register offsets for the Intel VT-d IOMMU.
- NumDomains
- CAP.ND encoding: number of supported domain IDs. §10.4.2, Table 10-2.
- Rtaddr
Reg - Root Table Address Register (MMIO offset 0x020, 64-bit, RW). §10.4.6.
- Translation
Table Mode - Translation table mode in RTADDR.TTM (§11.4.5).
- Version
Reg - Version Register (MMIO offset 0x000, 32-bit, RO). §10.4.1.
Constants§
- MMIO_
REGION_ SIZE - MMIO region size in bytes (4KB, one page).
- SLLPS_
1GB - CAP.SLLPS bit: 1GB large page support (30-bit page offset).
- SLLPS_
2MB - CAP.SLLPS bit: 2MB large page support (21-bit page offset).