Expand description
Definitions relating to the x86 architecture, including the core CPU and its interrupt controller (APIC).
Modules§
- apic
- APIC-related definitions.
- cpuid
- msi
- x86 definitions of non-translated MSI address and data.
- snp
- AMD SEV-SNP specific definitions.
- tdx
- Intel TDX specific definitions.
- vmx
- Intel VMX specific definitions.
- xsave
- Xsave-related definitions.
Structs§
- Exception
- GdtEntry
- IdtAttributes
- IdtEntry64
- Large
GdtEntry - Large
Pde - Misc
Enable - Values for
X86X_IA32_MSR_MISC_ENABLEMSR. - Page
Fault Error Code - Pte
- RFlags
- Segment
Attributes - Segment
Register - Segment
Selector - Segment selector (what goes into a segment register)
- Tss64
- X86x
McgStatus Register
Constants§
- DR6_
BREAKPOINT_ MASK - DR6_
SINGLE_ STEP - USER_
MODE_ DPL - X64_
BUSY_ TSS_ SEGMENT_ ATTRIBUTES - X64_
CR0_ AM - X64_
CR0_ CD - X64_
CR0_ EM - X64_
CR0_ ET - X64_
CR0_ MP - X64_
CR0_ NE - X64_
CR0_ NW - X64_
CR0_ PE - X64_
CR0_ PG - X64_
CR0_ TS - X64_
CR0_ WP - X64_
CR4_ CET - X64_
CR4_ DE - X64_
CR4_ FXSR - X64_
CR4_ LA57 - X64_
CR4_ MCE - X64_
CR4_ OSXSAVE - X64_
CR4_ PAE - X64_
CR4_ PCE - X64_
CR4_ PCIDE - X64_
CR4_ PGE - X64_
CR4_ PSE - X64_
CR4_ PVI - X64_
CR4_ RWFSGS - X64_
CR4_ SMAP - X64_
CR4_ SMEP - X64_
CR4_ TSD - X64_
CR4_ UMIP - X64_
CR4_ VME - X64_
CR4_ VMXE - X64_
CR4_ XMMEXCPT - X64_
DEFAULT_ CODE_ SEGMENT_ ATTRIBUTES - X64_
DEFAULT_ DATA_ SEGMENT_ ATTRIBUTES - X64_
EFER_ FFXSR - X64_
EFER_ LMA - X64_
EFER_ LME - X64_
EFER_ NXE - X64_
EFER_ SCE - X64_
EFER_ SVME - X64_
EMPTY_ DR7 - X64_
LARGE_ PAGE_ SIZE - X64_
MSR_ FS_ BASE - X64_
MSR_ GS_ BASE - X64_
MSR_ KERNEL_ GS_ BASE - X86X_
AMD_ MSR_ DE_ CFG - X86X_
AMD_ MSR_ GHCB - X86X_
AMD_ MSR_ HW_ CFG - X86X_
AMD_ MSR_ NB_ CFG - X86X_
AMD_ MSR_ OSVW_ ID_ LENGTH - X86X_
AMD_ MSR_ OSVW_ ID_ STATUS - X86X_
AMD_ MSR_ PERF_ CTR0 - X86X_
AMD_ MSR_ PERF_ CTR1 - X86X_
AMD_ MSR_ PERF_ CTR2 - X86X_
AMD_ MSR_ PERF_ CTR3 - X86X_
AMD_ MSR_ PERF_ EVT_ SEL0 - X86X_
AMD_ MSR_ PERF_ EVT_ SEL1 - X86X_
AMD_ MSR_ PERF_ EVT_ SEL2 - X86X_
AMD_ MSR_ PERF_ EVT_ SEL3 - X86X_
AMD_ MSR_ SEV - X86X_
AMD_ MSR_ SYSCFG - X86X_
AMD_ MSR_ VM_ CR - X86X_
IA32_ MSR_ DRAM_ ENERGY_ STATUS - X86X_
IA32_ MSR_ FEATURE_ CONTROL - X86X_
IA32_ MSR_ MISC_ ENABLE - X86X_
IA32_ MSR_ PKG_ ENERGY_ STATUS - X86X_
IA32_ MSR_ PLATFORM_ ID - X86X_
IA32_ MSR_ PP0_ ENERGY_ STATUS - X86X_
IA32_ MSR_ RAPL_ POWER_ UNIT - X86X_
IA32_ MSR_ SMI_ COUNT - X86X_
IA32_ MSR_ XFD - X86X_
IA32_ MSR_ XFD_ ERR - X86X_
MSR_ APIC_ BASE - X86X_
MSR_ BIOS_ UPDT_ TRIG - X86X_
MSR_ CR_ PAT - X86X_
MSR_ CSTAR - X86X_
MSR_ DEFAULT_ PAT - X86X_
MSR_ EBL_ CR_ POWERON - X86X_
MSR_ EFER - X86X_
MSR_ INTERRUPT_ SSP_ TABLE_ ADDR - X86X_
MSR_ LSTAR - X86X_
MSR_ MCG_ CAP - X86X_
MSR_ MCG_ STATUS - X86X_
MSR_ MC_ UPDATE_ PATCH_ LEVEL - X86X_
MSR_ MISC_ FEATURE_ ENABLES - X86X_
MSR_ MTRR_ CAP - X86X_
MSR_ MTRR_ DEF_ TYPE - X86X_
MSR_ MTRR_ FIX4K_ C0000 - X86X_
MSR_ MTRR_ FIX4K_ C8000 - X86X_
MSR_ MTRR_ FIX4K_ D0000 - X86X_
MSR_ MTRR_ FIX4K_ D8000 - X86X_
MSR_ MTRR_ FIX4K_ E0000 - X86X_
MSR_ MTRR_ FIX4K_ E8000 - X86X_
MSR_ MTRR_ FIX4K_ F0000 - X86X_
MSR_ MTRR_ FIX4K_ F8000 - X86X_
MSR_ MTRR_ FIX16K_ 80000 - X86X_
MSR_ MTRR_ FIX16K_ A0000 - X86X_
MSR_ MTRR_ FIX64K_ 00000 - X86X_
MSR_ MTRR_ PHYSBAS E0 - X86X_
MSR_ PL0_ SSP - X86X_
MSR_ PL1_ SSP - X86X_
MSR_ PL2_ SSP - X86X_
MSR_ PL3_ SSP - X86X_
MSR_ PLATFORM_ INFO - X86X_
MSR_ PPIN_ CTL - X86X_
MSR_ SFMASK - X86X_
MSR_ SPEC_ CTRL - X86X_
MSR_ STAR - X86X_
MSR_ SYSENTER_ CS - X86X_
MSR_ SYSENTER_ EIP - X86X_
MSR_ SYSENTER_ ESP - X86X_
MSR_ S_ CET - X86X_
MSR_ TSC - X86X_
MSR_ TSC_ AUX - X86X_
MSR_ UMWAIT_ CONTROL - X86X_
MSR_ U_ CET - X86X_
MSR_ XSS