Struct PciePortSettings 

pub struct PciePortSettings {
    pub acs_capabilities_supported: u16,
    pub cxl_flex_bus_port_capability: Option<CxlFlexBusPortDvsecCapability>,
}

Express-level settings for a PCIe port.

Collects feature flags that apply uniformly to a port so that adding new capabilities does not require changing every constructor signature.

Fields

acs_capabilities_supported: u16

ACS capability bits to advertise on this port. 0 means the ACS extended capability is not present.

cxl_flex_bus_port_capability: Option<CxlFlexBusPortDvsecCapability>

Flex Bus Port capability bits used to advertise CXL support on ports.

CXL DVSECs are added only when this is Some and either cache_capable or mem_capable is set.

Trait Implementations

impl Clone for PciePortSettings

fn clone(&self) -> PciePortSettings

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for PciePortSettings

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for PciePortSettings

fn default() -> PciePortSettings

Returns the “default value” for a type.