LinkWidth

pci_core::spec::caps::pci_express

Enum LinkWidth 

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#[repr(u32)]
pub enum LinkWidth {
    X1 = 1,
    X2 = 2,
    X4 = 4,
    X8 = 8,
    X16 = 16,
}
Expand description

PCIe Link Width encoding values for use in Link Capabilities and other registers.

Values are defined in PCIe Base Specification for the Max Link Width field in Link Capabilities Register and similar fields.

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X1 = 1

x1 link width

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X2 = 2

x2 link width

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X4 = 4

x4 link width

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X8 = 8

x8 link width

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X16 = 16

x16 link width

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impl LinkWidth

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pub const fn from_bits(bits: u32) -> Self

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pub const fn into_bits(self) -> u32

Trait Implementations§

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impl Debug for LinkWidth

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

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