pub struct DmaTarget { /* private fields */ }Expand description
Everything a PCI device needs for bus-mastered transactions: DMA memory access and MSI interrupt delivery.
Most devices only need guest_memory and
msi_target. SR-IOV PFs additionally call
with_rid_offset when creating VFs.
Implementations§
Source§impl DmaTarget
impl DmaTarget
Sourcepub fn new(
bus_range: AssignedBusRange,
devfn: u8,
guest_memory: GuestMemory,
msi: &MsiConnection,
) -> Self
pub fn new( bus_range: AssignedBusRange, devfn: u8, guest_memory: GuestMemory, msi: &MsiConnection, ) -> Self
Creates a DMA target with no IOMMU.
bus_range and devfn set the device’s requester-ID identity, shared
by both the DMA and MSI sides. The MSI backend is taken (late-bound)
from msi. Since there is no IOMMU, all targets derived from this one
share the same guest memory; with_rid_offset
only updates the MSI identity.
Sourcepub fn with_iommu(
bus_range: AssignedBusRange,
devfn: u8,
iommu: Arc<dyn DmaTargetIommu>,
msi: &MsiConnection,
) -> Self
pub fn with_iommu( bus_range: AssignedBusRange, devfn: u8, iommu: Arc<dyn DmaTargetIommu>, msi: &MsiConnection, ) -> Self
Creates a DMA target backed by a software/emulated IOMMU.
The base (function-devfn) translating guest memory is derived from
iommu; per-VF memory is produced by
with_rid_offset. The MSI backend is taken
(late-bound) from msi.
The device is marked DmaPassthrough::SoftwareBlocked: a
software/emulated IOMMU cannot program the host IOMMU, so host
passthrough (VFIO assignment) is rejected. Use
with_nestable_iommu for a
hardware-nestable IOMMU that permits passthrough.
Sourcepub fn with_nestable_iommu(
bus_range: AssignedBusRange,
devfn: u8,
iommu: Arc<dyn DmaTargetIommu>,
handle: Arc<dyn Any + Send + Sync>,
msi: &MsiConnection,
) -> Self
pub fn with_nestable_iommu( bus_range: AssignedBusRange, devfn: u8, iommu: Arc<dyn DmaTargetIommu>, handle: Arc<dyn Any + Send + Sync>, msi: &MsiConnection, ) -> Self
Creates a DMA target backed by a hardware-nestable IOMMU.
Like with_iommu, but marks the device
DmaPassthrough::HardwareNestable with an opaque handle that the
host-assignment backend downcasts to its arch-specific nesting context.
Accel-capable IOMMUs (e.g. an SMMU that programs the host IOMMU for
nested stage-1 translation) use this to permit VFIO passthrough despite
wrapping guest memory with a translating target; the handle carries
everything the backend needs to wire the device into the emulated IOMMU.
Supplying the nesting handle together with the iommu is what makes a
DmaPassthrough::HardwareNestable target impossible to construct
without a backing IOMMU.
Sourcepub fn guest_memory(&self) -> &GuestMemory
pub fn guest_memory(&self) -> &GuestMemory
Returns the guest memory for DMA from this device.
Sourcepub fn msi_target(&self) -> &MsiTarget
pub fn msi_target(&self) -> &MsiTarget
Returns the MSI target for interrupt delivery from this device.
Sourcepub fn passthrough(&self) -> DmaPassthrough<'_>
pub fn passthrough(&self) -> DmaPassthrough<'_>
The device’s host-passthrough disposition.
Used by host-assignment backends (e.g. the VFIO resolver) to decide whether the device may be passed through and, when it is behind a hardware-nestable IOMMU, to obtain the opaque handle they downcast to attach to the emulated IOMMU.
Sourcepub fn with_rid_offset(&self, delta: u16) -> DmaTarget
pub fn with_rid_offset(&self, delta: u16) -> DmaTarget
Derives a DMA target offset by delta from this one in RID space.
This is the SR-IOV VF derivation primitive: given a PF’s target, its
ith VF is delta = VF_Offset + i * VF_Stride away. Offsets stack,
so deriving from an already-derived target accumulates. Both the DMA
and MSI identity are derived in lockstep and resolved at use time as
(secondary << 8) + offset against the live bus assignment, so VF
targets can be derived before the bus is programmed.