Trait pci_bus::GenericPciBusDevice

pub trait GenericPciBusDevice: 'static + Send {
    // Required methods
    fn pci_cfg_read(&mut self, offset: u16, value: &mut u32) -> Option<IoResult>;
    fn pci_cfg_write(&mut self, offset: u16, value: u32) -> Option<IoResult>;
}

An abstract interface for a PCI device accessed via the GenericPciBus.

This trait is nearly identical to [chipset_device::pci::PciConfigSpace], except for the fact that the return values are wrapped in an Option, where None indicates that the backing device is no longer responding to accesses.

e.g: a GenericPciBusDevice backed by a Weak pointer to a device could get invalidated, in which case, these APIs would return None.

This trait decouples the PCI bus implementation from any concrete ChipsetDevice ownership model being employed by upper-level code (i.e: Arc/Weak + Mutex vs. Channels, etc…).

This is also the reason why the read/write methods are fallible: the PCI bus should be resilient to backing devices unexpectedly going offline.

Required Methods

fn pci_cfg_read(&mut self, offset: u16, value: &mut u32) -> Option<IoResult>

Dispatch a PCI config space read to the device with the given address.

fn pci_cfg_write(&mut self, offset: u16, value: u32) -> Option<IoResult>

Dispatch a PCI config space write to the device with the given address.

Implementors