Struct PciePortConfig 

pub struct PciePortConfig {
    pub name: String,
    pub devfn: Option<u8>,
    pub hotplug: bool,
    pub acs_capabilities_supported: Option<u16>,
    pub cxl: bool,
}

Configuration for a single PCIe port — either a root-complex root port or a switch downstream port.

Fields

name: String

Port name used for topology wiring and lookup.

devfn: Option<u8>

The device/function (device << 3 | function) to place this port at on its bus.

When None, the port is assigned the lowest available devfn. Ports are assigned in order, so an explicit devfn that collides with a previously-assigned port (including one assigned automatically) is an error. Honored for both root-complex root ports and switch downstream ports.

hotplug: bool

Enables PCIe hotplug capabilities for this port.

acs_capabilities_supported: Option<u16>

Optional ACS capability bitmask to expose on this port.

cxl: bool

Marks this port as CXL-capable.

Runtime port construction derives required BAR/subregion layout from this flag (currently CXL component registers for BAR0).

Trait Implementations

impl Debug for PciePortConfig

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl DefaultEncoding for PciePortConfig

type Encoding = TableEncoder

The encoding to use for the serialization.

impl<'encoding> StructDecodeMetadata<'encoding, Resource> for PciePortConfig

const DECODERS: &'static [ErasedDecoderEntry]

The list of decoder vtables.

impl StructEncodeMetadata<Resource> for PciePortConfig

const ENCODERS: &'static [ErasedEncoderEntry]

The list of encoder vtables.

impl StructMetadata for PciePortConfig

const NUMBERS: &'static [u32]

The field numbers for each field.

const OFFSETS: &'static [usize]

The byte offset to each field within the struct.