Module pte 

Second-level page table entry types for the Intel VT-d IOMMU.

Based on Intel VT-d Specification Rev 4.1, §9.8. The second-level page table format is EPT-like: 64-bit entries, 9 bits per level, with R/W permission bits in bits 1:0 (bit 2 is ignored) and a PS bit at bit 7 for large pages at levels 2 (2MB) and 3 (1GB). Accessed (bit 8) and leaf dirty (bit 9) flags are ignored unless Second Stage Access/Dirty bit Enable (SSADE) is set in the referencing scalable-mode PASID-table entry (§3.7.2).

Page table level parameters:

• Level 4: VA[47:39], 9 bits → 512GB region
• Level 3: VA[38:30], 9 bits → 1GB page (if PS=1)
• Level 2: VA[29:21], 9 bits → 2MB page (if PS=1)
• Level 1: VA[20:12], 9 bits → 4KB page

Structs

SlPte

A 64-bit second-level page table entry (PTE or PDE).

Constants

BITS_PER_LEVEL

Bits per page table level index (log2 of 512 = 9).

ENTRIES_PER_TABLE

Number of entries per page table page (4KB / 8 bytes = 512).

PAGE_SIZE_1G

Page size at level 3 (1GB).

PAGE_SIZE_2M

Page size at level 2 (2MB).

PAGE_SIZE_4K

Page size at level 1 (4KB).