hv1_emulator::synic

Struct ProcessorSynic

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pub struct ProcessorSynic { /* private fields */ }
Expand description

The virtual processor synthetic interrupt controller state.

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impl ProcessorSynic

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pub fn reset(&mut self)

Resets the synic state back to its initial state.

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pub fn siefp(&self) -> u64

Returns the event flags page register.

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pub fn simp(&self) -> u64

Returns the message page register.

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pub fn scontrol(&self) -> u64

Returns the SCONTROL register.

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pub fn sversion(&self) -> u64

Returns the SVERSION register.

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pub fn eom(&self) -> u64

Returns the end-of-message register.

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pub fn sint(&self, n: u8) -> u64

Returns the specified SINT register.

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pub fn proxied_sints(&self) -> u16

Returns the set of SINTs that are proxied to the host.

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pub fn stimer_config(&self, n: usize) -> u64

Returns the specified synthetic timer configuration register.

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pub fn stimer_count(&self, n: usize) -> u64

Returns the specified synthetic timer count register.

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pub fn vina(&self) -> HvRegisterVsmVina

Returns the value of the VINA register.

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pub fn set_siefp(&mut self, v: u64)

Sets the event flags page register.

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pub fn set_simp(&mut self, v: u64)

Sets the message page register.

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pub fn set_scontrol(&mut self, v: u64)

Sets the SCONTROL register.

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pub fn set_eom(&mut self, _v: u64)

Performs an end-of-message operation.

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pub fn set_sint(&mut self, n: usize, v: u64)

Sets the specified SINT register.

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pub fn set_stimer_config(&mut self, n: usize, v: u64)

Sets the specified synthetic timer configuration register.

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pub fn set_stimer_count(&mut self, n: usize, v: u64)

Sets the specified synthetic timer count register.

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pub fn request_sint_readiness(&mut self, sints: u16)

Requests a notification when any of the requested sints has a free message slot.

The free sints will be returned by Self::scan.

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pub fn post_message( &mut self, sint_index: u8, message: &HvMessage, interrupt: &mut dyn RequestInterrupt, ) -> Result<(), HvError>

Writes a message to the message page.

Returns Err(HvError::ObjectInUse) if the message slot is full.

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pub fn write_reg( &mut self, reg: HvRegisterName, v: HvRegisterValue, ) -> HvResult<()>

Writes a synthetic interrupt controller register.

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pub fn write_msr(&mut self, msr: u32, v: u64) -> Result<(), MsrError>

Writes an x64 MSR.

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pub fn write_nontimer_msr(&mut self, msr: u32, v: u64) -> Result<(), MsrError>

Writes a non-synthetic-timer x64 MSR.

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pub fn read_reg(&self, reg: HvRegisterName) -> HvResult<HvRegisterValue>

Reads a synthetic interrupt controller register.

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pub fn read_msr(&self, msr: u32) -> Result<u64, MsrError>

Reads an x64 MSR.

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pub fn read_nontimer_msr(&self, msr: u32) -> Result<u64, MsrError>

Reads a non-synthetic-timer x64 MSR.

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pub fn scan( &mut self, ref_time_now: u64, interrupt: &mut dyn RequestInterrupt, ) -> (u16, Option<u64>)

Scans for pending messages and timers.

Calls interrupt with the APIC vector to signal, possibly multiple times for different SINTs.

Returns SINTs that are now deliverable after calls to Self::request_sint_readiness.

Trait Implementations§

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impl Inspect for ProcessorSynic

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fn inspect(&self, req: Request<'_>)

Inspects the object.

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