Struct ProcessorSynic

pub struct ProcessorSynic { /* private fields */ }

The virtual processor synthetic interrupt controller state.

Implementations

impl ProcessorSynic

pub fn reset(&mut self)

Resets the synic state back to its initial state.

pub fn siefp(&self) -> u64

Returns the event flags page register.

pub fn simp(&self) -> u64

Returns the message page register.

pub fn scontrol(&self) -> u64

Returns the SCONTROL register.

pub fn sversion(&self) -> u64

Returns the SVERSION register.

pub fn eom(&self) -> u64

Returns the end-of-message register.

pub fn sint(&self, n: u8) -> u64

Returns the specified SINT register.

pub fn proxied_sints(&self) -> u16

Returns the set of SINTs that are proxied to the host.

pub fn stimer_config(&self, n: usize) -> u64

Returns the specified synthetic timer configuration register.

pub fn stimer_count(&self, n: usize) -> u64

Returns the specified synthetic timer count register.

pub fn vina(&self) -> HvRegisterVsmVina

Returns the value of the VINA register.

pub fn set_siefp( &mut self, v: u64, prot_access: &mut dyn VtlProtectAccess, ) -> Result<(), MsrError>

Sets the event flags page register.

pub fn set_simp( &mut self, v: u64, prot_access: &mut dyn VtlProtectAccess, ) -> Result<(), MsrError>

Sets the message page register.

pub fn set_scontrol(&mut self, v: u64)

Sets the SCONTROL register.

pub fn set_eom(&mut self, _v: u64)

Performs an end-of-message operation.

pub fn set_sint(&mut self, n: usize, v: u64)

Sets the specified SINT register.

pub fn set_stimer_config(&mut self, n: usize, v: u64)

Sets the specified synthetic timer configuration register.

pub fn set_stimer_count(&mut self, n: usize, v: u64)

Sets the specified synthetic timer count register.

pub fn request_sint_readiness(&mut self, sints: u16)

Requests a notification when any of the requested sints has a free message slot.

The free sints will be returned by Self::scan.

pub fn post_message( &mut self, sint_index: u8, message: &HvMessage, interrupt: &mut dyn RequestInterrupt, ) -> Result<(), HvError>

Writes a message to the message page.

Returns Err(HvError::ObjectInUse) if the message slot is full.

pub fn post_intercept_message( &mut self, message: &HvMessage, interrupt: &mut dyn RequestInterrupt, ) -> Result<(), HvError>

Writes an intercept message to the message page. Meant to be used on paths where the message can be written directly without using the message queues, as it marks the intercept sint as ready.

Returns Err(HvError::ObjectInUse) if the message slot is full.

pub fn write_reg( &mut self, reg: HvRegisterName, v: HvRegisterValue, prot_access: &mut dyn VtlProtectAccess, ) -> HvResult<()>

Writes a synthetic interrupt controller register.

pub fn write_msr( &mut self, msr: u32, v: u64, prot_access: &mut dyn VtlProtectAccess, ) -> Result<(), MsrError>

Writes an x64 MSR.

pub fn write_nontimer_msr( &mut self, msr: u32, v: u64, prot_access: &mut dyn VtlProtectAccess, ) -> Result<(), MsrError>

Writes a non-synthetic-timer x64 MSR.

pub fn read_reg(&self, reg: HvRegisterName) -> HvResult<HvRegisterValue>

Reads a synthetic interrupt controller register.

pub fn read_msr(&self, msr: u32) -> Result<u64, MsrError>

Reads an x64 MSR.

pub fn read_nontimer_msr(&self, msr: u32) -> Result<u64, MsrError>

Reads a non-synthetic-timer x64 MSR.

pub fn scan( &mut self, ref_time_now: u64, interrupt: &mut dyn RequestInterrupt, ) -> (u16, Option<u64>)

Scans for pending messages and timers.

Calls interrupt with the APIC vector to signal, possibly multiple times for different SINTs.

Returns SINTs that are now deliverable after calls to Self::request_sint_readiness.

Trait Implementations

impl Inspect for ProcessorSynic

fn inspect(&self, req: Request<'_>)

Inspects the object.