whp/
abi.rs

1// Copyright (c) Microsoft Corporation.
2// Licensed under the MIT License.
3
4#![expect(non_camel_case_types, non_snake_case, non_upper_case_globals)]
5
6mod arm64;
7mod x64;
8
9#[cfg(target_arch = "aarch64")]
10pub use arm64::*;
11#[cfg(target_arch = "x86_64")]
12pub use x64::*;
13
14use std::ffi::c_void;
15use std::fmt::Debug;
16use std::fmt::Display;
17use windows_sys::Win32::Foundation::LUID;
18
19macro_rules! bitops_base {
20    ($t:ty) => {
21        impl std::ops::BitOr for $t {
22            type Output = Self;
23            fn bitor(mut self, rhs: Self) -> Self {
24                self |= rhs;
25                self
26            }
27        }
28
29        impl std::ops::BitAnd for $t {
30            type Output = Self;
31            fn bitand(mut self, rhs: Self) -> Self {
32                self &= rhs;
33                self
34            }
35        }
36    };
37}
38
39#[cfg(target_arch = "x86_64")]
40pub(crate) use bitops_base;
41
42macro_rules! bitops {
43    ($t:ty) => {
44        bitops_base!($t);
45        impl $t {
46            pub fn is_empty(&self) -> bool {
47                self.0 == 0
48            }
49            pub fn is_set(&self, v: Self) -> bool {
50                self.0 & v.0 == v.0
51            }
52        }
53        impl std::ops::BitOrAssign for $t {
54            fn bitor_assign(&mut self, rhs: Self) {
55                self.0 |= rhs.0;
56            }
57        }
58        impl std::ops::BitAndAssign for $t {
59            fn bitand_assign(&mut self, rhs: Self) {
60                self.0 &= rhs.0;
61            }
62        }
63        impl std::ops::Not for $t {
64            type Output = Self;
65
66            fn not(self) -> Self {
67                Self(!self.0)
68            }
69        }
70    };
71}
72
73#[cfg(target_arch = "x86_64")]
74pub(crate) use bitops;
75
76#[repr(C)]
77#[derive(Copy, Clone, Debug, PartialEq, Eq)]
78pub struct WHV_CAPABILITY_CODE(pub u32);
79
80// Capabilities of the API implementation
81pub const WHvCapabilityCodeHypervisorPresent: WHV_CAPABILITY_CODE = WHV_CAPABILITY_CODE(0x00000000);
82pub const WHvCapabilityCodeFeatures: WHV_CAPABILITY_CODE = WHV_CAPABILITY_CODE(0x00000001);
83pub const WHvCapabilityCodeExtendedVmExits: WHV_CAPABILITY_CODE = WHV_CAPABILITY_CODE(0x00000002);
84#[cfg(target_arch = "x86_64")]
85pub const WHvCapabilityCodeExceptionExitBitmap: WHV_CAPABILITY_CODE =
86    WHV_CAPABILITY_CODE(0x00000003);
87#[cfg(target_arch = "x86_64")]
88pub const WHvCapabilityCodeX64MsrExitBitmap: WHV_CAPABILITY_CODE = WHV_CAPABILITY_CODE(0x00000004);
89pub const WHvCapabilityCodeGpaRangePopulateFlags: WHV_CAPABILITY_CODE =
90    WHV_CAPABILITY_CODE(0x00000005);
91pub const WHvCapabilityCodeSchedulerFeatures: WHV_CAPABILITY_CODE = WHV_CAPABILITY_CODE(0x00000006);
92
93// Capabilities of the system's processor
94pub const WHvCapabilityCodeProcessorVendor: WHV_CAPABILITY_CODE = WHV_CAPABILITY_CODE(0x00001000);
95pub const WHvCapabilityCodeProcessorFeatures: WHV_CAPABILITY_CODE = WHV_CAPABILITY_CODE(0x00001001);
96pub const WHvCapabilityCodeProcessorClFlushSize: WHV_CAPABILITY_CODE =
97    WHV_CAPABILITY_CODE(0x00001002);
98#[cfg(target_arch = "x86_64")]
99pub const WHvCapabilityCodeProcessorXsaveFeatures: WHV_CAPABILITY_CODE =
100    WHV_CAPABILITY_CODE(0x00001003);
101pub const WHvCapabilityCodeProcessorClockFrequency: WHV_CAPABILITY_CODE =
102    WHV_CAPABILITY_CODE(0x00001004);
103#[cfg(target_arch = "x86_64")]
104pub const WHvCapabilityCodeInterruptClockFrequency: WHV_CAPABILITY_CODE =
105    WHV_CAPABILITY_CODE(0x00001005);
106pub const WHvCapabilityCodeProcessorFeaturesBanks: WHV_CAPABILITY_CODE =
107    WHV_CAPABILITY_CODE(0x00001006);
108pub const WHvCapabilityCodeProcessorFrequencyCap: WHV_CAPABILITY_CODE =
109    WHV_CAPABILITY_CODE(0x00001007);
110pub const WHvCapabilityCodeSyntheticProcessorFeaturesBanks: WHV_CAPABILITY_CODE =
111    WHV_CAPABILITY_CODE(0x00001008);
112#[cfg(target_arch = "x86_64")]
113pub const WHvCapabilityCodePerfmonFeatures: WHV_CAPABILITY_CODE = WHV_CAPABILITY_CODE(0x00001009);
114
115pub struct WHV_CAPABILITY_FEATURES(pub u64);
116bitops!(WHV_CAPABILITY_FEATURES);
117
118impl WHV_CAPABILITY_FEATURES {
119    pub const PartialUnmap: Self = Self(1 << 0);
120    #[cfg(target_arch = "x86_64")]
121    pub const LocalApicEmulation: Self = Self(1 << 1);
122    #[cfg(target_arch = "x86_64")]
123    pub const Xsave: Self = Self(1 << 2);
124    pub const DirtyPageTracking: Self = Self(1 << 3);
125    pub const SpeculationControl: Self = Self(1 << 4);
126    #[cfg(target_arch = "x86_64")]
127    pub const ApicRemoteRead: Self = Self(1 << 5);
128    pub const IdleSuspend: Self = Self(1 << 6);
129    pub const VirtualPciDeviceSupport: Self = Self(1 << 7);
130    pub const IommuSupport: Self = Self(1 << 8);
131    pub const VpHotAddSupport: Self = Self(1 << 9);
132}
133
134#[repr(C)]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub struct WHV_PROCESSOR_VENDOR(pub u32);
137
138pub const WHvProcessorVendorAmd: WHV_PROCESSOR_VENDOR = WHV_PROCESSOR_VENDOR(0x0000);
139pub const WHvProcessorVendorIntel: WHV_PROCESSOR_VENDOR = WHV_PROCESSOR_VENDOR(0x0001);
140pub const WHvProcessorVendorHygon: WHV_PROCESSOR_VENDOR = WHV_PROCESSOR_VENDOR(0x0002);
141pub const WHvProcessorVendorArm: WHV_PROCESSOR_VENDOR = WHV_PROCESSOR_VENDOR(0x0010);
142
143#[repr(C)]
144#[derive(Debug, Copy, Clone)]
145pub struct WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP {
146    pub Flags: u32,
147    pub HighestFrequencyMhz: u32,
148    pub NominalFrequencyMhz: u32,
149    pub LowestFrequencyMhz: u32,
150    pub FrequencyStepMhz: u32,
151}
152
153impl WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP {
154    pub fn IsSupported(&self) -> bool {
155        (self.Flags & 1) != 0
156    }
157}
158
159#[repr(C)]
160#[derive(Clone, Copy)]
161pub struct WHV_PARTITION_HANDLE(pub isize);
162
163impl Debug for WHV_PARTITION_HANDLE {
164    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
165        f.debug_struct("WHV_PARTITION_HANDLE").finish()
166    }
167}
168
169#[repr(C)]
170#[derive(Debug, Copy, Clone)]
171pub struct WHV_MAP_GPA_RANGE_FLAGS(pub u32);
172bitops!(WHV_MAP_GPA_RANGE_FLAGS);
173
174pub const WHvMapGpaRangeFlagNone: WHV_MAP_GPA_RANGE_FLAGS = WHV_MAP_GPA_RANGE_FLAGS(0x00000000);
175pub const WHvMapGpaRangeFlagRead: WHV_MAP_GPA_RANGE_FLAGS = WHV_MAP_GPA_RANGE_FLAGS(0x00000001);
176pub const WHvMapGpaRangeFlagWrite: WHV_MAP_GPA_RANGE_FLAGS = WHV_MAP_GPA_RANGE_FLAGS(0x00000002);
177pub const WHvMapGpaRangeFlagExecute: WHV_MAP_GPA_RANGE_FLAGS = WHV_MAP_GPA_RANGE_FLAGS(0x00000004);
178pub const WHvMapGpaRangeFlagTrackDirtyPages: WHV_MAP_GPA_RANGE_FLAGS =
179    WHV_MAP_GPA_RANGE_FLAGS(0x00000008);
180
181#[repr(transparent)]
182#[derive(Debug, Copy, Clone)]
183pub struct WHV_PARTITION_PROPERTY_CODE(u32);
184
185pub const WHvPartitionPropertyCodeExtendedVmExits: WHV_PARTITION_PROPERTY_CODE =
186    WHV_PARTITION_PROPERTY_CODE(0x00000001);
187#[cfg(target_arch = "x86_64")]
188pub const WHvPartitionPropertyCodeExceptionExitBitmap: WHV_PARTITION_PROPERTY_CODE =
189    WHV_PARTITION_PROPERTY_CODE(0x00000002);
190pub const WHvPartitionPropertyCodeSeparateSecurityDomain: WHV_PARTITION_PROPERTY_CODE =
191    WHV_PARTITION_PROPERTY_CODE(0x00000003);
192#[cfg(target_arch = "x86_64")]
193pub const WHvPartitionPropertyCodeX64MsrExitBitmap: WHV_PARTITION_PROPERTY_CODE =
194    WHV_PARTITION_PROPERTY_CODE(0x00000005);
195pub const WHvPartitionPropertyCodePrimaryNumaNode: WHV_PARTITION_PROPERTY_CODE =
196    WHV_PARTITION_PROPERTY_CODE(0x00000006);
197pub const WHvPartitionPropertyCodeCpuReserve: WHV_PARTITION_PROPERTY_CODE =
198    WHV_PARTITION_PROPERTY_CODE(0x00000007);
199pub const WHvPartitionPropertyCodeCpuCap: WHV_PARTITION_PROPERTY_CODE =
200    WHV_PARTITION_PROPERTY_CODE(0x00000008);
201pub const WHvPartitionPropertyCodeCpuWeight: WHV_PARTITION_PROPERTY_CODE =
202    WHV_PARTITION_PROPERTY_CODE(0x00000009);
203pub const WHvPartitionPropertyCodeCpuGroupId: WHV_PARTITION_PROPERTY_CODE =
204    WHV_PARTITION_PROPERTY_CODE(0x0000000a);
205pub const WHvPartitionPropertyCodeProcessorFrequencyCap: WHV_PARTITION_PROPERTY_CODE =
206    WHV_PARTITION_PROPERTY_CODE(0x0000000b);
207pub const WHvPartitionPropertyCodeAllowDeviceAssignment: WHV_PARTITION_PROPERTY_CODE =
208    WHV_PARTITION_PROPERTY_CODE(0x0000000c);
209pub const WHvPartitionPropertyCodeDisableSmt: WHV_PARTITION_PROPERTY_CODE =
210    WHV_PARTITION_PROPERTY_CODE(0x0000000d);
211
212pub const WHvPartitionPropertyCodeProcessorFeatures: WHV_PARTITION_PROPERTY_CODE =
213    WHV_PARTITION_PROPERTY_CODE(0x00001001);
214pub const WHvPartitionPropertyCodeProcessorClFlushSize: WHV_PARTITION_PROPERTY_CODE =
215    WHV_PARTITION_PROPERTY_CODE(0x00001002);
216#[cfg(target_arch = "x86_64")]
217pub const WHvPartitionPropertyCodeCpuidExitList: WHV_PARTITION_PROPERTY_CODE =
218    WHV_PARTITION_PROPERTY_CODE(0x00001003);
219#[cfg(target_arch = "x86_64")]
220pub const WHvPartitionPropertyCodeCpuidResultList: WHV_PARTITION_PROPERTY_CODE =
221    WHV_PARTITION_PROPERTY_CODE(0x00001004);
222#[cfg(target_arch = "x86_64")]
223pub const WHvPartitionPropertyCodeLocalApicEmulationMode: WHV_PARTITION_PROPERTY_CODE =
224    WHV_PARTITION_PROPERTY_CODE(0x00001005);
225#[cfg(target_arch = "x86_64")]
226pub const WHvPartitionPropertyCodeProcessorXsaveFeatures: WHV_PARTITION_PROPERTY_CODE =
227    WHV_PARTITION_PROPERTY_CODE(0x00001006);
228pub const WHvPartitionPropertyCodeProcessorClockFrequency: WHV_PARTITION_PROPERTY_CODE =
229    WHV_PARTITION_PROPERTY_CODE(0x00001007);
230#[cfg(target_arch = "x86_64")]
231pub const WHvPartitionPropertyCodeInterruptClockFrequency: WHV_PARTITION_PROPERTY_CODE =
232    WHV_PARTITION_PROPERTY_CODE(0x00001008);
233#[cfg(target_arch = "x86_64")]
234pub const WHvPartitionPropertyCodeApicRemoteReadSupport: WHV_PARTITION_PROPERTY_CODE =
235    WHV_PARTITION_PROPERTY_CODE(0x00001009);
236pub const WHvPartitionPropertyCodeProcessorFeaturesBanks: WHV_PARTITION_PROPERTY_CODE =
237    WHV_PARTITION_PROPERTY_CODE(0x0000100A);
238pub const WHvPartitionPropertyCodeReferenceTime: WHV_PARTITION_PROPERTY_CODE =
239    WHV_PARTITION_PROPERTY_CODE(0x0000100B);
240pub const WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks: WHV_PARTITION_PROPERTY_CODE =
241    WHV_PARTITION_PROPERTY_CODE(0x0000100C);
242#[cfg(target_arch = "x86_64")]
243pub const WHvPartitionPropertyCodeCpuidResultList2: WHV_PARTITION_PROPERTY_CODE =
244    WHV_PARTITION_PROPERTY_CODE(0x0000100D);
245#[cfg(target_arch = "x86_64")]
246pub const WHvPartitionPropertyCodeProcessorPerfmonFeatures: WHV_PARTITION_PROPERTY_CODE =
247    WHV_PARTITION_PROPERTY_CODE(0x0000100E);
248#[cfg(target_arch = "x86_64")]
249pub const WHvPartitionPropertyCodeMsrActionList: WHV_PARTITION_PROPERTY_CODE =
250    WHV_PARTITION_PROPERTY_CODE(0x0000100F);
251#[cfg(target_arch = "x86_64")]
252pub const WHvPartitionPropertyCodeUnimplementedMsrAction: WHV_PARTITION_PROPERTY_CODE =
253    WHV_PARTITION_PROPERTY_CODE(0x00001010);
254pub const WHvPartitionPropertyCodePhysicalAddressWidth: WHV_PARTITION_PROPERTY_CODE =
255    WHV_PARTITION_PROPERTY_CODE(0x00001011);
256pub const WHvPartitionPropertyCodeArm64IcParameters: WHV_PARTITION_PROPERTY_CODE =
257    WHV_PARTITION_PROPERTY_CODE(0x00001012);
258pub const WHvPartitionPropertyCodeProcessorCount: WHV_PARTITION_PROPERTY_CODE =
259    WHV_PARTITION_PROPERTY_CODE(0x00001fff);
260
261#[repr(transparent)]
262#[derive(Clone, Copy, Debug, Eq, PartialEq)]
263pub struct WHV_REGISTER_NAME(pub u32);
264
265#[repr(C)]
266#[derive(Clone, Copy, Debug, Eq, PartialEq, Default)]
267pub struct WHV_REGISTER_VALUE(pub WHV_UINT128);
268
269#[repr(transparent)]
270#[derive(Debug, Copy, Clone)]
271pub struct WHV_ADVISE_GPA_RANGE_CODE(u32);
272
273pub const WHvAdviseGpaRangeCodePopulate: WHV_ADVISE_GPA_RANGE_CODE =
274    WHV_ADVISE_GPA_RANGE_CODE(0x00000000);
275pub const WHvAdviseGpaRangeCodePin: WHV_ADVISE_GPA_RANGE_CODE =
276    WHV_ADVISE_GPA_RANGE_CODE(0x00000001);
277pub const WHvAdviseGpaRangeCodeUnpin: WHV_ADVISE_GPA_RANGE_CODE =
278    WHV_ADVISE_GPA_RANGE_CODE(0x00000002);
279
280#[repr(C)]
281#[derive(Copy, Clone)]
282pub struct WHV_RUN_VP_EXIT_CONTEXT {
283    pub ExitReason: WHV_RUN_VP_EXIT_REASON,
284    pub Reserved: u32,
285    #[cfg(target_arch = "x86_64")]
286    pub VpContext: WHV_VP_EXIT_CONTEXT,
287    #[cfg(all(target_arch = "aarch64", feature = "unstable_whp"))]
288    pub Reserved1: u64,
289    pub u: WHV_RUN_VP_EXIT_CONTEXT_u,
290}
291
292#[repr(C)]
293#[derive(Debug, Copy, Clone, Default)]
294pub struct WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS(pub u32);
295bitops!(WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS);
296
297impl WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS {
298    pub const Prefetch: Self = Self(0x1);
299    pub const AvoidHardFaults: Self = Self(0x2);
300}
301
302#[repr(C)]
303#[derive(Debug, Copy, Clone)]
304pub struct WHV_ADVISE_GPA_RANGE_POPULATE {
305    pub Flags: WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS,
306    pub AccessType: WHV_MEMORY_ACCESS_TYPE,
307}
308
309#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)]
310pub struct WHV_EXTENDED_VM_EXITS(pub u64);
311bitops!(WHV_EXTENDED_VM_EXITS);
312
313impl WHV_EXTENDED_VM_EXITS {
314    #[cfg(target_arch = "x86_64")]
315    pub const X64CpuidExit: Self = Self(1 << 0);
316    #[cfg(target_arch = "x86_64")]
317    pub const X64MsrExit: Self = Self(1 << 1);
318    #[cfg(target_arch = "x86_64")]
319    pub const ExceptionExit: Self = Self(1 << 2);
320    #[cfg(target_arch = "x86_64")]
321    pub const X64RdtscExit: Self = Self(1 << 3);
322    #[cfg(target_arch = "x86_64")]
323    pub const X64ApicSmiExitTrap: Self = Self(1 << 4);
324    pub const HypercallExit: Self = Self(1 << 5);
325    #[cfg(target_arch = "x86_64")]
326    pub const X64ApicInitSipiExitTrap: Self = Self(1 << 6);
327    #[cfg(target_arch = "x86_64")]
328    pub const X64ApicWriteLint0ExitTrap: Self = Self(1 << 7);
329    #[cfg(target_arch = "x86_64")]
330    pub const X64ApicWriteLint1ExitTrap: Self = Self(1 << 8);
331    #[cfg(target_arch = "x86_64")]
332    pub const X64ApicWriteSvrExitTrap: Self = Self(1 << 9);
333    pub const UnknownSynicConnection: Self = Self(1 << 10);
334    pub const RetargetUnknownVpciDevice: Self = Self(1 << 11);
335    #[cfg(target_arch = "x86_64")]
336    pub const X64ApicWriteLdrExitTrap: Self = Self(1 << 12);
337    #[cfg(target_arch = "x86_64")]
338    pub const X64ApicWriteDfrExitTrap: Self = Self(1 << 13);
339    pub const GpaAccessFaultExit: Self = Self(1 << 14);
340}
341
342#[repr(C)]
343#[derive(Debug, Copy, Clone)]
344pub struct WHV_PROCESSOR_FEATURES_BANKS {
345    pub BanksCount: u32,
346    pub Reserved0: u32,
347    pub Banks: [u64; 2],
348}
349
350#[derive(Debug, Copy, Clone, Default, Eq, PartialEq)]
351pub struct WHV_PROCESSOR_FEATURES(pub u64);
352bitops!(WHV_PROCESSOR_FEATURES);
353
354#[repr(C)]
355#[derive(Debug, Copy, Clone, Default, Eq, PartialEq)]
356pub struct WHV_PROCESSOR_FEATURES1(pub u64);
357bitops!(WHV_PROCESSOR_FEATURES1);
358
359#[derive(Debug, Copy, Clone)]
360pub struct WHV_PROCESSOR_XSAVE_FEATURES(pub u64);
361bitops!(WHV_PROCESSOR_XSAVE_FEATURES);
362
363impl WHV_PROCESSOR_XSAVE_FEATURES {
364    pub const XsaveSupport: Self = Self(1 << 0);
365    pub const XsaveoptSupport: Self = Self(1 << 1);
366    pub const AvxSupport: Self = Self(1 << 2);
367    pub const Avx2Support: Self = Self(1 << 3);
368    pub const FmaSupport: Self = Self(1 << 4);
369    pub const MpxSupport: Self = Self(1 << 5);
370    pub const Avx512Support: Self = Self(1 << 6);
371    pub const Avx512DqSupport: Self = Self(1 << 7);
372    pub const Avx512CdSupport: Self = Self(1 << 8);
373    pub const Avx512BwSupport: Self = Self(1 << 9);
374    pub const Avx512VlSupport: Self = Self(1 << 10);
375    pub const XsaveCompSupport: Self = Self(1 << 11);
376    pub const XsaveSupervisorSupport: Self = Self(1 << 12);
377    pub const Xcr1Support: Self = Self(1 << 13);
378    pub const Avx512BitalgSupport: Self = Self(1 << 14);
379    pub const Avx512IfmaSupport: Self = Self(1 << 15);
380    pub const Avx512VBmiSupport: Self = Self(1 << 16);
381    pub const Avx512VBmi2Support: Self = Self(1 << 17);
382    pub const Avx512VnniSupport: Self = Self(1 << 18);
383    pub const GfniSupport: Self = Self(1 << 19);
384    pub const VaesSupport: Self = Self(1 << 20);
385    pub const Avx512VPopcntdqSupport: Self = Self(1 << 21);
386    pub const VpclmulqdqSupport: Self = Self(1 << 22);
387    pub const Avx512Bf16Support: Self = Self(1 << 23);
388    pub const Avx512Vp2IntersectSupport: Self = Self(1 << 24);
389    pub const Avx512Fp16Support: Self = Self(1 << 25);
390    pub const XfdSupport: Self = Self(1 << 26);
391    pub const AmxTileSupport: Self = Self(1 << 27);
392    pub const AmxBf16Support: Self = Self(1 << 28);
393    pub const AmxInt8Support: Self = Self(1 << 29);
394    pub const AvxVnniSupport: Self = Self(1 << 30);
395}
396
397#[derive(Debug, Default, Copy, Clone, Eq, PartialEq)]
398pub struct WHV_SYNTHETIC_PROCESSOR_FEATURES(pub u64);
399bitops!(WHV_SYNTHETIC_PROCESSOR_FEATURES);
400
401impl WHV_SYNTHETIC_PROCESSOR_FEATURES {
402    /// Report a hypervisor is present. CPUID leaves
403    /// 0x40000000 and 0x40000001 are supported.
404    pub const HypervisorPresent: Self = Self(1 << 0);
405
406    /// Report support for Hv1 (CPUID leaves 0x40000000 - 0x40000006).
407    pub const Hv1: Self = Self(1 << 1);
408
409    /// Access to HV_X64_MSR_VP_RUNTIME.
410    /// Corresponds to AccessVpRunTimeReg privilege.
411    pub const AccessVpRunTimeReg: Self = Self(1 << 2);
412
413    /// Access to HV_X64_MSR_TIME_REF_COUNT.
414    /// Corresponds to AccessPartitionReferenceCounter privilege.
415    pub const AccessPartitionReferenceCounter: Self = Self(1 << 3);
416
417    /// Access to SINT-related registers (HV_X64_MSR_SCONTROL through
418    /// HV_X64_MSR_EOM and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15).
419    /// Corresponds to AccessSynicRegs privilege.
420    pub const AccessSynicRegs: Self = Self(1 << 4);
421
422    /// Access to synthetic timers and associated MSRs
423    /// (HV_X64_MSR_STIMER0_CONFIG through HV_X64_MSR_STIMER3_COUNT).
424    /// Corresponds to AccessSyntheticTimerRegs privilege.
425    pub const AccessSyntheticTimerRegs: Self = Self(1 << 5);
426
427    /// Access to APIC MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
428    /// as well as the VP assist page.
429    /// Corresponds to AccessIntrCtrlRegs privilege.
430    pub const AccessIntrCtrlRegs: Self = Self(1 << 6);
431
432    /// Access to registers associated with hypercalls (HV_X64_MSR_GUEST_OS_ID
433    /// and HV_X64_MSR_HYPERCALL).
434    /// Corresponds to AccessHypercallMsrs privilege.
435    pub const AccessHypercallRegs: Self = Self(1 << 7);
436
437    /// VP index can be queried. Corresponds to AccessVpIndex privilege.
438    pub const AccessVpIndex: Self = Self(1 << 8);
439
440    /// Access to the reference TSC. Corresponds to AccessPartitionReferenceTsc
441    /// privilege.
442    pub const AccessPartitionReferenceTsc: Self = Self(1 << 9);
443
444    /// Partition has access to the guest idle reg. Corresponds to
445    /// AccessGuestIdleReg privilege.
446    ///
447    #[cfg(target_arch = "x86_64")]
448    pub const AccessGuestIdleReg: Self = Self(1 << 10);
449
450    /// Partition has access to frequency regs. Corresponds to AccessFrequencyRegs
451    /// privilege.
452    #[cfg(target_arch = "x86_64")]
453    pub const AccessFrequencyRegs: Self = Self(1 << 11);
454
455    // pub const ReservedZ12: Self = Self(1 << 12);
456    // pub const ReservedZ13: Self = Self(1 << 13);
457    // pub const ReservedZ14: Self = Self(1 << 14);
458
459    /// Extended GVA ranges for HvCallFlushVirtualAddressList hypercall.
460    /// Corresponds to privilege.
461    #[cfg(target_arch = "x86_64")]
462    pub const EnableExtendedGvaRangesForFlushVirtualAddressList: Self = Self(1 << 15);
463
464    // pub const ReservedZ16: Self = Self(1 << 16);
465    // pub const ReservedZ17: Self = Self(1 << 17);
466
467    /// Use fast hypercall output. Corresponds to privilege.
468    pub const FastHypercallOutput: Self = Self(1 << 18);
469
470    // pub const ReservedZ19: Self = Self(1 << 19);
471
472    // pub const ReservedZ20: Self = Self(1 << 20);
473
474    // pub const ReservedZ21: Self = Self(1 << 21);
475
476    /// Synthetic timers in direct mode.
477    pub const DirectSyntheticTimers: Self = Self(1 << 22);
478
479    // pub const ReservedZ23: Self = Self(1 << 23);
480
481    /// Use extended processor masks.
482    pub const ExtendedProcessorMasks: Self = Self(1 << 24);
483
484    // On AMD64, HvCallFlushVirtualAddressSpace / HvCallFlushVirtualAddressList are supported, on
485    // ARM64 HvCallFlushVirtualAddressSpace / HvCallFlushTlb are supported.
486    pub const TbFlushHypercalls: Self = Self(1 << 25);
487
488    /// HvCallSendSyntheticClusterIpi is supported.
489    pub const SyntheticClusterIpi: Self = Self(1 << 26);
490
491    /// HvCallNotifyLongSpinWait is supported.
492    pub const NotifyLongSpinWait: Self = Self(1 << 27);
493
494    /// HvCallQueryNumaDistance is supported.
495    pub const QueryNumaDistance: Self = Self(1 << 28);
496
497    /// HvCallSignalEvent is supported. Corresponds to privilege.
498    pub const SignalEvents: Self = Self(1 << 29);
499
500    /// HvCallRetargetDeviceInterrupt is supported.
501    pub const RetargetDeviceInterrupt: Self = Self(1 << 30);
502
503    /// HvCallRestorePartitionTime is supported.
504    #[cfg(target_arch = "x86_64")]
505    pub const RestoreTime: Self = Self(1 << 31);
506
507    /// EnlightenedVmcs nested enlightenment is supported.
508    #[cfg(target_arch = "x86_64")]
509    pub const EnlightenedVmcs: Self = Self(1 << 32);
510
511    /// Non-zero values can be written to DEBUG_CTL.
512    #[cfg(target_arch = "x86_64")]
513    pub const NestedDebugCtl: Self = Self(1 << 33);
514
515    /// Synthetic time-unhalted timer MSRs are supported.
516    #[cfg(target_arch = "x86_64")]
517    pub const SyntheticTimeUnhaltedTimer: Self = Self(1 << 34);
518
519    /// SPEC_CTRL MSR behavior when the VP is idle
520    #[cfg(target_arch = "x86_64")]
521    pub const IdleSpecCtrl: Self = Self(1 << 35);
522
523    /// Register intercepts supported in V1. As more registers are supported in the future
524    /// releases, new bits will be added here to prevent migration between incompatible hosts.
525    ///
526    /// List of registers supported in V1.
527    /// 1. TPIDRRO_EL0
528    /// 2. TPIDR_EL1
529    /// 3. SCTLR_EL1 - Supports write intercept mask.
530    /// 4. VBAR_EL1
531    /// 5. TCR_EL1 - Supports write intercept mask.
532    /// 6. MAIR_EL1 - Supports write intercept mask.
533    /// 7. CPACR_EL1 - Supports write intercept mask.
534    /// 8. CONTEXTIDR_EL1
535    /// 9. PAuth keys(total 10 registers)
536    /// 10. HvArm64RegisterSyntheticException
537    #[cfg(target_arch = "aarch64")]
538    pub const RegisterInterceptsV1: Self = Self(1 << 36);
539
540    /// HvCallWakeVps is supported.
541    pub const WakeVps: Self = Self(1 << 37);
542
543    /// HvCallGet/SetVpRegisters is supported.
544    /// Corresponds to the AccessVpRegisters privilege.
545    /// This feature only affects exo partitions.
546    pub const AccessVpRegs: Self = Self(1 << 38);
547
548    /// HvCallSyncContext/Ex is supported.
549    #[cfg(target_arch = "aarch64")]
550    pub const SyncContext: Self = Self(1 << 39);
551
552    /// Management VTL synic support is allowed.
553    /// Corresponds to the ManagementVtlSynicSupport privilege.
554    pub const ManagementVtlSynicSupport: Self = Self(1 << 40);
555
556    /// Hypervisor supports guest mechanism to signal pending interrupts to paravisor.
557    #[cfg(target_arch = "x86_64")]
558    pub const ProxyInterruptDoorbellSupport: Self = Self(1 << 41);
559
560    /// InterceptSystemResetAvailable is exposed.
561    #[cfg(target_arch = "aarch64")]
562    pub const InterceptSystemReset: Self = Self(1 << 42);
563
564    /// Hypercalls for host MMIO operations are available.
565    pub const MmioHypercalls: Self = Self(1 << 43);
566
567    /// SPIs are advertised to VTL2.
568    #[cfg(target_arch = "aarch64")]
569    pub const ManagementVtlSpiSupport: Self = Self(1 << 44);
570}
571
572#[repr(C)]
573#[derive(Debug, Copy, Clone)]
574pub struct WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS {
575    pub BanksCount: u32,
576    pub Reserved0: u32,
577    pub Banks: [u64; 1],
578}
579
580#[repr(C)]
581#[derive(Debug, Copy, Clone)]
582pub struct WHV_TRANSLATE_GVA_RESULT {
583    pub ResultCode: WHV_TRANSLATE_GVA_RESULT_CODE,
584    pub Reserved: u32,
585}
586
587#[repr(transparent)]
588#[derive(Debug, Copy, Clone, PartialEq, Eq)]
589pub struct WHV_TRANSLATE_GVA_FLAGS(pub u32);
590bitops!(WHV_TRANSLATE_GVA_FLAGS);
591
592pub const WHvTranslateGvaFlagNone: WHV_TRANSLATE_GVA_FLAGS = WHV_TRANSLATE_GVA_FLAGS(0x00000000);
593pub const WHvTranslateGvaFlagValidateRead: WHV_TRANSLATE_GVA_FLAGS =
594    WHV_TRANSLATE_GVA_FLAGS(0x00000001);
595pub const WHvTranslateGvaFlagValidateWrite: WHV_TRANSLATE_GVA_FLAGS =
596    WHV_TRANSLATE_GVA_FLAGS(0x00000002);
597pub const WHvTranslateGvaFlagValidateExecute: WHV_TRANSLATE_GVA_FLAGS =
598    WHV_TRANSLATE_GVA_FLAGS(0x00000004);
599#[cfg(target_arch = "x86_64")]
600pub const WHvTranslateGvaFlagPrivilegeExempt: WHV_TRANSLATE_GVA_FLAGS =
601    WHV_TRANSLATE_GVA_FLAGS(0x00000008);
602pub const WHvTranslateGvaFlagSetPageTableBits: WHV_TRANSLATE_GVA_FLAGS =
603    WHV_TRANSLATE_GVA_FLAGS(0x00000010);
604
605#[repr(C)]
606#[derive(Debug, Copy, Clone, PartialEq, Eq)]
607pub struct WHV_TRANSLATE_GVA_RESULT_CODE(pub u32);
608
609pub const WHvTranslateGvaResultSuccess: WHV_TRANSLATE_GVA_RESULT_CODE =
610    WHV_TRANSLATE_GVA_RESULT_CODE(0);
611
612// Translation failures
613pub const WHvTranslateGvaResultPageNotPresent: WHV_TRANSLATE_GVA_RESULT_CODE =
614    WHV_TRANSLATE_GVA_RESULT_CODE(1);
615pub const WHvTranslateGvaResultPrivilegeViolation: WHV_TRANSLATE_GVA_RESULT_CODE =
616    WHV_TRANSLATE_GVA_RESULT_CODE(2);
617pub const WHvTranslateGvaResultInvalidPageTableFlags: WHV_TRANSLATE_GVA_RESULT_CODE =
618    WHV_TRANSLATE_GVA_RESULT_CODE(3);
619
620// GPA access failures
621pub const WHvTranslateGvaResultGpaUnmapped: WHV_TRANSLATE_GVA_RESULT_CODE =
622    WHV_TRANSLATE_GVA_RESULT_CODE(4);
623pub const WHvTranslateGvaResultGpaNoReadAccess: WHV_TRANSLATE_GVA_RESULT_CODE =
624    WHV_TRANSLATE_GVA_RESULT_CODE(5);
625pub const WHvTranslateGvaResultGpaNoWriteAccess: WHV_TRANSLATE_GVA_RESULT_CODE =
626    WHV_TRANSLATE_GVA_RESULT_CODE(6);
627pub const WHvTranslateGvaResultGpaIllegalOverlayAccess: WHV_TRANSLATE_GVA_RESULT_CODE =
628    WHV_TRANSLATE_GVA_RESULT_CODE(7);
629pub const WHvTranslateGvaResultIntercept: WHV_TRANSLATE_GVA_RESULT_CODE =
630    WHV_TRANSLATE_GVA_RESULT_CODE(8);
631
632#[repr(C)]
633#[derive(Debug, Copy, Clone)]
634pub struct WHV_DOORBELL_MATCH_DATA {
635    pub GuestAddress: u64,
636    pub Value: u64,
637    pub Length: u32,
638    pub Flags: u32,
639}
640
641#[repr(C)]
642#[derive(Debug, Copy, Clone)]
643pub struct WHV_MEMORY_RANGE_ENTRY {
644    pub GuestAddress: u64,
645    pub SizeInBytes: u64,
646}
647
648#[repr(C)]
649#[derive(Debug, Copy, Clone)]
650pub struct WHV_SYNIC_EVENT_PARAMETERS {
651    pub VpIndex: u32,
652    pub TargetSint: u8,
653    pub Reserved: u8,
654    pub FlagNumber: u16,
655}
656
657#[repr(C)]
658#[derive(Debug, Copy, Clone, PartialEq, Eq)]
659pub struct WHV_RUN_VP_EXIT_REASON(pub u32);
660
661#[repr(transparent)]
662#[derive(Debug, Copy, Clone, PartialEq, Eq)]
663pub struct WHV_MEMORY_ACCESS_TYPE(pub u32);
664
665pub const WHvMemoryAccessRead: WHV_MEMORY_ACCESS_TYPE = WHV_MEMORY_ACCESS_TYPE(0);
666pub const WHvMemoryAccessWrite: WHV_MEMORY_ACCESS_TYPE = WHV_MEMORY_ACCESS_TYPE(1);
667pub const WHvMemoryAccessExecute: WHV_MEMORY_ACCESS_TYPE = WHV_MEMORY_ACCESS_TYPE(2);
668
669impl Display for WHV_MEMORY_ACCESS_TYPE {
670    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
671        let string = match *self {
672            WHvMemoryAccessRead => "read",
673            WHvMemoryAccessWrite => "write",
674            WHvMemoryAccessExecute => "execute",
675            _ => "unknown",
676        };
677
678        f.write_str(string)
679    }
680}
681
682#[repr(C, align(16))]
683#[derive(Default, Debug, Copy, Clone, PartialEq, Eq)]
684pub struct WHV_UINT128([u8; 16]);
685
686impl From<u128> for WHV_UINT128 {
687    fn from(v: u128) -> Self {
688        Self(v.to_ne_bytes())
689    }
690}
691
692impl From<u64> for WHV_UINT128 {
693    fn from(v: u64) -> Self {
694        (v as u128).into()
695    }
696}
697
698impl From<u32> for WHV_UINT128 {
699    fn from(v: u32) -> Self {
700        (v as u128).into()
701    }
702}
703
704impl From<u16> for WHV_UINT128 {
705    fn from(v: u16) -> Self {
706        (v as u128).into()
707    }
708}
709
710impl From<u8> for WHV_UINT128 {
711    fn from(v: u8) -> Self {
712        (v as u128).into()
713    }
714}
715
716impl From<WHV_UINT128> for u128 {
717    fn from(v: WHV_UINT128) -> Self {
718        u128::from_ne_bytes(v.0)
719    }
720}
721
722#[repr(C)]
723#[derive(Debug, Copy, Clone)]
724pub struct WHV_NOTIFICATION_PORT_HANDLE(pub isize);
725
726#[repr(C)]
727#[derive(Debug, Copy, Clone)]
728pub struct WHV_NOTIFICATION_PORT_PROPERTY_CODE(pub u32);
729
730pub const WHvNotificationPortPropertyPreferredTargetVp: WHV_NOTIFICATION_PORT_PROPERTY_CODE =
731    WHV_NOTIFICATION_PORT_PROPERTY_CODE(1);
732pub const WHvNotificationPortPropertyPreferredTargetDuration: WHV_NOTIFICATION_PORT_PROPERTY_CODE =
733    WHV_NOTIFICATION_PORT_PROPERTY_CODE(5);
734
735#[repr(C)]
736#[derive(Debug, Copy, Clone)]
737pub struct WHV_NOTIFICATION_PORT_TYPE(pub u32);
738
739pub const WHvNotificationPortTypeEvent: WHV_NOTIFICATION_PORT_TYPE = WHV_NOTIFICATION_PORT_TYPE(2);
740pub const WHvNotificationPortTypeDoorbell: WHV_NOTIFICATION_PORT_TYPE =
741    WHV_NOTIFICATION_PORT_TYPE(4);
742
743#[repr(C)]
744#[derive(Copy, Clone)]
745pub struct WHV_NOTIFICATION_PORT_PARAMETERS {
746    pub NotificationPortType: WHV_NOTIFICATION_PORT_TYPE,
747    pub Reserved: u32,
748    pub u: WHV_NOTIFICATION_PORT_PARAMETERS_u,
749}
750
751#[repr(C)]
752#[derive(Copy, Clone)]
753pub union WHV_NOTIFICATION_PORT_PARAMETERS_u {
754    pub Doorbell: WHV_DOORBELL_MATCH_DATA,
755    pub Event: WHV_NOTIFICATION_PORT_PARAMETERS_u_Event,
756}
757
758#[repr(C)]
759#[derive(Copy, Clone)]
760pub struct WHV_NOTIFICATION_PORT_PARAMETERS_u_Event {
761    pub ConnectionId: u32,
762}
763
764#[repr(C)]
765#[derive(Debug, Copy, Clone)]
766pub struct WHV_CPUID_OUTPUT {
767    pub Eax: u32,
768    pub Ebx: u32,
769    pub Ecx: u32,
770    pub Edx: u32,
771}
772
773#[repr(C)]
774#[derive(Debug, Copy, Clone)]
775pub struct WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE(u32);
776
777pub const WHvVirtualProcessorPropertyCodeNumaNode: WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE =
778    WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE(0x00000000);
779
780#[repr(C)]
781#[derive(Copy, Clone)]
782pub struct WHV_VIRTUAL_PROCESSOR_PROPERTY {
783    pub PropertyCode: WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE,
784    pub Reserved: u32,
785    pub u: WHV_VIRTUAL_PROCESSOR_PROPERTY_u,
786}
787
788#[repr(C)]
789#[derive(Copy, Clone)]
790pub union WHV_VIRTUAL_PROCESSOR_PROPERTY_u {
791    pub NumaNode: u16,
792    pub Padding: u64,
793}
794
795#[repr(C)]
796#[derive(Debug, Copy, Clone)]
797pub struct WHV_MSR_ACTION_ENTRY {
798    pub Index: u32,
799    pub ReadAction: u8,  // WHV_MSR_ACTION
800    pub WriteAction: u8, // WHV_MSR_ACTION
801    pub Reserved: u16,
802}
803
804#[repr(C)]
805#[derive(Debug, Copy, Clone)]
806pub struct WHV_MSR_ACTION(pub u32);
807
808pub const WHvMsrActionArchitectureDefault: WHV_MSR_ACTION = WHV_MSR_ACTION(0);
809pub const WHvMsrActionIgnoreWriteReadZero: WHV_MSR_ACTION = WHV_MSR_ACTION(1);
810pub const WHvMsrActionExit: WHV_MSR_ACTION = WHV_MSR_ACTION(2);
811
812#[repr(C)]
813#[derive(Debug, Copy, Clone)]
814pub struct WHV_SCHEDULER_FEATURES(pub u32);
815bitops!(WHV_SCHEDULER_FEATURES);
816
817impl WHV_SCHEDULER_FEATURES {
818    pub const CpuReserve: Self = Self(1 << 0);
819    pub const CpuCap: Self = Self(1 << 1);
820    pub const CpuWeight: Self = Self(1 << 2);
821    pub const CpuGroupId: Self = Self(1 << 3);
822    pub const DisableSmt: Self = Self(1 << 4);
823}
824
825#[repr(C)]
826#[derive(Debug, Clone, Copy, Default)]
827pub struct WHV_ALLOCATE_VPCI_RESOURCE_FLAGS(pub u32);
828bitops!(WHV_ALLOCATE_VPCI_RESOURCE_FLAGS);
829
830pub const WHvAllocateVpciResourceFlagAllowDirectP2P: WHV_ALLOCATE_VPCI_RESOURCE_FLAGS =
831    WHV_ALLOCATE_VPCI_RESOURCE_FLAGS(0x00000001);
832
833pub const WHV_MAX_DEVICE_ID_SIZE_IN_CHARS: usize = 200;
834
835#[repr(C)]
836#[derive(Clone, Copy)]
837pub struct WHV_SRIOV_RESOURCE_DESCRIPTOR {
838    pub PnpInstanceId: [u16; WHV_MAX_DEVICE_ID_SIZE_IN_CHARS],
839    pub VirtualFunctionId: LUID,
840    pub VirtualFunctionIndex: u16,
841    pub Reserved: u16,
842}
843
844#[repr(C)]
845#[derive(Debug, Clone, Copy, PartialEq, Eq)]
846pub struct WHV_VPCI_DEVICE_NOTIFICATION_TYPE(pub u32);
847
848pub const WHvVpciDeviceNotificationUndefined: WHV_VPCI_DEVICE_NOTIFICATION_TYPE =
849    WHV_VPCI_DEVICE_NOTIFICATION_TYPE(0);
850pub const WHvVpciDeviceNotificationMmioRemapping: WHV_VPCI_DEVICE_NOTIFICATION_TYPE =
851    WHV_VPCI_DEVICE_NOTIFICATION_TYPE(1);
852pub const WHvVpciDeviceNotificationSurpriseRemoval: WHV_VPCI_DEVICE_NOTIFICATION_TYPE =
853    WHV_VPCI_DEVICE_NOTIFICATION_TYPE(2);
854
855#[repr(C)]
856#[derive(Debug, Clone, Copy)]
857pub struct WHV_VPCI_DEVICE_NOTIFICATION {
858    pub NotificationType: WHV_VPCI_DEVICE_NOTIFICATION_TYPE,
859    pub Reserved1: u32,
860    pub Reserved2: u64,
861}
862
863#[repr(C)]
864#[derive(Debug, Clone, Copy, Default)]
865pub struct WHV_CREATE_VPCI_DEVICE_FLAGS(u32);
866bitops!(WHV_CREATE_VPCI_DEVICE_FLAGS);
867
868pub const WHvCreateVpciDeviceFlagNone: WHV_CREATE_VPCI_DEVICE_FLAGS =
869    WHV_CREATE_VPCI_DEVICE_FLAGS(0x00000000);
870pub const WHvCreateVpciDeviceFlagPhysicallyBacked: WHV_CREATE_VPCI_DEVICE_FLAGS =
871    WHV_CREATE_VPCI_DEVICE_FLAGS(0x00000001);
872pub const WHvCreateVpciDeviceFlagUseLogicalInterrupts: WHV_CREATE_VPCI_DEVICE_FLAGS =
873    WHV_CREATE_VPCI_DEVICE_FLAGS(0x00000002);
874
875#[repr(C)]
876#[derive(Debug, Clone, Copy)]
877pub struct WHV_VPCI_DEVICE_PROPERTY_CODE(u32);
878
879pub const WHvVpciDevicePropertyCodeUndefined: WHV_VPCI_DEVICE_PROPERTY_CODE =
880    WHV_VPCI_DEVICE_PROPERTY_CODE(0);
881pub const WHvVpciDevicePropertyCodeHardwareIDs: WHV_VPCI_DEVICE_PROPERTY_CODE =
882    WHV_VPCI_DEVICE_PROPERTY_CODE(1);
883pub const WHvVpciDevicePropertyCodeProbedBARs: WHV_VPCI_DEVICE_PROPERTY_CODE =
884    WHV_VPCI_DEVICE_PROPERTY_CODE(2);
885
886#[repr(C)]
887#[derive(Debug, Clone, Copy, Default)]
888pub struct WHV_VPCI_HARDWARE_IDS {
889    pub VendorID: u16,
890    pub DeviceID: u16,
891    pub RevisionID: u8,
892    pub ProgIf: u8,
893    pub SubClass: u8,
894    pub BaseClass: u8,
895    pub SubVendorID: u16,
896    pub SubSystemID: u16,
897}
898
899#[repr(C)]
900#[derive(Debug, Clone, Copy, Default)]
901pub struct WHV_VPCI_PROBED_BARS {
902    pub Value: [u32; 6],
903}
904
905#[repr(C)]
906#[derive(Debug, Clone, Copy, Default)]
907pub struct WHV_VPCI_MMIO_RANGE_FLAGS(pub u32);
908bitops!(WHV_VPCI_MMIO_RANGE_FLAGS);
909
910pub const WHvVpciMmioRangeFlagReadAccess: WHV_VPCI_MMIO_RANGE_FLAGS =
911    WHV_VPCI_MMIO_RANGE_FLAGS(0x00000001);
912pub const WHvVpciMmioRangeFlagWriteAccess: WHV_VPCI_MMIO_RANGE_FLAGS =
913    WHV_VPCI_MMIO_RANGE_FLAGS(0x00000002);
914
915#[repr(C)]
916#[derive(Debug, Clone, Copy)]
917pub struct WHV_VPCI_DEVICE_REGISTER_SPACE(pub i32);
918
919pub const WHvVpciConfigSpace: WHV_VPCI_DEVICE_REGISTER_SPACE = WHV_VPCI_DEVICE_REGISTER_SPACE(-1);
920pub const WHvVpciBar0: WHV_VPCI_DEVICE_REGISTER_SPACE = WHV_VPCI_DEVICE_REGISTER_SPACE(0);
921pub const WHvVpciBar1: WHV_VPCI_DEVICE_REGISTER_SPACE = WHV_VPCI_DEVICE_REGISTER_SPACE(1);
922pub const WHvVpciBar2: WHV_VPCI_DEVICE_REGISTER_SPACE = WHV_VPCI_DEVICE_REGISTER_SPACE(2);
923pub const WHvVpciBar3: WHV_VPCI_DEVICE_REGISTER_SPACE = WHV_VPCI_DEVICE_REGISTER_SPACE(3);
924pub const WHvVpciBar4: WHV_VPCI_DEVICE_REGISTER_SPACE = WHV_VPCI_DEVICE_REGISTER_SPACE(4);
925pub const WHvVpciBar5: WHV_VPCI_DEVICE_REGISTER_SPACE = WHV_VPCI_DEVICE_REGISTER_SPACE(5);
926
927#[repr(C)]
928#[derive(Debug, Clone, Copy)]
929pub struct WHV_VPCI_MMIO_MAPPING {
930    pub Location: WHV_VPCI_DEVICE_REGISTER_SPACE,
931    pub Flags: WHV_VPCI_MMIO_RANGE_FLAGS,
932    pub SizeInBytes: u64,
933    pub OffsetInBytes: u64,
934    pub VirtualAddress: *mut c_void,
935}
936
937#[repr(C)]
938#[derive(Debug, Clone, Copy)]
939pub struct WHV_VPCI_DEVICE_REGISTER {
940    pub Location: WHV_VPCI_DEVICE_REGISTER_SPACE,
941    pub SizeInBytes: u32,
942    pub OffsetInBytes: u64,
943}
944
945#[repr(C)]
946#[derive(Debug, Clone, Copy)]
947pub struct WHV_VPCI_INTERRUPT_TARGET {
948    pub Vector: u32,
949    pub Flags: WHV_VPCI_INTERRUPT_TARGET_FLAGS,
950    pub ProcessorCount: u32,
951    pub Processors: [u32; 0],
952}
953
954#[repr(C)]
955#[derive(Debug, Copy, Clone, Default)]
956pub struct WHV_VPCI_INTERRUPT_TARGET_FLAGS(pub u32);
957bitops!(WHV_VPCI_INTERRUPT_TARGET_FLAGS);
958
959pub const WHvVpciInterruptTargetFlagMulticast: WHV_VPCI_INTERRUPT_TARGET_FLAGS =
960    WHV_VPCI_INTERRUPT_TARGET_FLAGS(1);
961
962#[repr(C)]
963#[derive(Copy, Clone, Debug)]
964pub struct WHV_TRIGGER_TYPE(u32);
965
966pub const WHvTriggerTypeInterrupt: WHV_TRIGGER_TYPE = WHV_TRIGGER_TYPE(0);
967pub const WHvTriggerTypeSynicEvent: WHV_TRIGGER_TYPE = WHV_TRIGGER_TYPE(1);
968pub const WHvTriggerTypeDeviceInterrupt: WHV_TRIGGER_TYPE = WHV_TRIGGER_TYPE(2);
969
970#[repr(C)]
971#[derive(Copy, Clone)]
972pub struct WHV_TRIGGER_PARAMETERS {
973    pub TriggerType: WHV_TRIGGER_TYPE,
974    pub Reserved: u32,
975    pub u: WHV_TRIGGER_PARAMETERS_u,
976}
977
978#[repr(C)]
979#[derive(Copy, Clone)]
980pub union WHV_TRIGGER_PARAMETERS_u {
981    #[cfg(target_arch = "x86_64")]
982    pub Interrupt: WHV_INTERRUPT_CONTROL,
983    pub SynicEvent: WHV_SYNIC_EVENT_PARAMETERS,
984    pub DeviceInterrupt: WHV_TRIGGER_PARAMETERS_u_DeviceInterrupt,
985}
986
987#[repr(C)]
988#[derive(Debug, Copy, Clone)]
989pub struct WHV_TRIGGER_PARAMETERS_u_DeviceInterrupt {
990    pub LogicalDeviceId: u64,
991    pub MsiAddress: u64,
992    pub MsiData: u32,
993    pub Reserved: u32,
994}
995
996#[repr(C)]
997#[derive(Debug, Copy, Clone)]
998pub struct WHV_TRIGGER_HANDLE(isize);
999
1000#[repr(transparent)]
1001#[derive(Debug, Copy, Clone)]
1002pub struct WHV_VIRTUAL_PROCESSOR_STATE_TYPE(u32);
1003
1004pub const WHvVirtualProcessorStateTypeSynicMessagePage: WHV_VIRTUAL_PROCESSOR_STATE_TYPE =
1005    WHV_VIRTUAL_PROCESSOR_STATE_TYPE(0x00000000);
1006pub const WHvVirtualProcessorStateTypeSynicEventFlagPage: WHV_VIRTUAL_PROCESSOR_STATE_TYPE =
1007    WHV_VIRTUAL_PROCESSOR_STATE_TYPE(0x00000001);
1008pub const WHvVirtualProcessorStateTypeSynicTimerState: WHV_VIRTUAL_PROCESSOR_STATE_TYPE =
1009    WHV_VIRTUAL_PROCESSOR_STATE_TYPE(0x00000002);
1010pub const WHvVirtualProcessorStateTypeInterruptControllerState2: WHV_VIRTUAL_PROCESSOR_STATE_TYPE =
1011    WHV_VIRTUAL_PROCESSOR_STATE_TYPE(0x00001000);
1012pub const WHvVirtualProcessorStateTypeXsaveState: WHV_VIRTUAL_PROCESSOR_STATE_TYPE =
1013    WHV_VIRTUAL_PROCESSOR_STATE_TYPE(0x00001001);
1014
1015#[repr(u32)]
1016#[derive(Debug, Copy, Clone)]
1017pub enum WHV_ARM64_IC_EMULATION_MODE {
1018    None = 0,
1019    GicV3 = 1,
1020}
1021
1022#[repr(C, packed)]
1023#[derive(Debug, Copy, Clone)]
1024pub struct WHV_ARM64_IC_GIC_V3_PARAMETERS {
1025    pub GicdBaseAddress: u64,
1026    pub GitsTranslatorBaseAddress: u64,
1027    pub Reserved: u32,
1028    pub GicLpiIntIdBits: u32,
1029    pub GicPpiOverflowInterruptFromCntv: u32,
1030    pub GicPpiPerformanceMonitorsInterrupt: u32,
1031    pub Reserved1: [u32; 6],
1032}
1033
1034// Legacy Hyper-V defaults
1035pub const DEFAULT_GITS_TRANSLATER_BASE_ADDRESS: u64 = 0;
1036pub const DEFAULT_GIC_LPI_INT_ID_BITS: u32 = 1;
1037pub const DEFAULT_GIC_PPI_OVERFLOW_INTERRUPT_FROM_CNTV: u32 = 0x14;
1038
1039#[repr(C, packed)]
1040#[derive(Debug, Copy, Clone)]
1041pub struct WHV_ARM64_IC_PARAMETERS {
1042    pub EmulationMode: WHV_ARM64_IC_EMULATION_MODE,
1043    pub Reserved: u32,
1044    pub GicV3Parameters: WHV_ARM64_IC_GIC_V3_PARAMETERS,
1045}
whp/abi.rs

whp/
abi.rs
