loader\uefi/
mod.rs

1// Copyright (c) Microsoft Corporation.
2// Licensed under the MIT License.
3
4//! UEFI specific loader definitions and implementation.
5
6pub mod config;
7
8#[cfg(guest_arch = "aarch64")]
9use aarch64 as arch;
10#[cfg(guest_arch = "x86_64")]
11use x86_64 as arch;
12
13pub use arch::CONFIG_BLOB_GPA_BASE;
14pub use arch::IMAGE_SIZE;
15pub use arch::load;
16
17use guid::Guid;
18use thiserror::Error;
19use zerocopy::FromBytes;
20use zerocopy::Immutable;
21use zerocopy::IntoBytes;
22use zerocopy::KnownLayout;
23
24// Constant defining the offset within the image where the SEC volume starts.
25// TODO: Revisit this when we reorganize the firmware layout. One option
26// would be to just put the SEC volume at the start of the image, so no need
27// for this offset.
28const SEC_FIRMWARE_VOLUME_OFFSET: u64 = 0x005E0000;
29
30/// Expand a 3 byte sequence into little-endian integer.
31fn expand_3byte_integer(size: [u8; 3]) -> u64 {
32    ((size[2] as u64) << 16) + ((size[1] as u64) << 8) + size[0] as u64
33}
34
35const fn signature_16(v: &[u8; 2]) -> u16 {
36    v[0] as u16 | (v[1] as u16) << 8
37}
38
39const fn signature_32(v: &[u8; 4]) -> u32 {
40    v[0] as u32 | (v[1] as u32) << 8 | (v[2] as u32) << 16 | (v[3] as u32) << 24
41}
42
43const IMAGE_DOS_SIGNATURE: u16 = 0x5A4D; // MZ
44const IMAGE_NT_SIGNATURE: u32 = 0x00004550; // PE00
45const TE_IMAGE_HEADER_SIGNATURE: u16 = signature_16(b"VZ");
46const EFI_FVH_SIGNATURE: u32 = signature_32(b"_FVH");
47
48#[repr(C)]
49#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
50struct ImageDosHeader {
51    e_magic: u16,      // Magic number
52    e_cblp: u16,       // Bytes on last page of file
53    e_cp: u16,         // Pages in file
54    e_crlc: u16,       // Relocations
55    e_cparhdr: u16,    // Size of header in paragraphs
56    e_minalloc: u16,   // Minimum extra paragraphs needed
57    e_maxalloc: u16,   // Maximum extra paragraphs needed
58    e_ss: u16,         // Initial (relative) SS value
59    e_sp: u16,         // Initial SP value
60    e_csum: u16,       // Checksum
61    e_ip: u16,         // Initial IP value
62    e_cs: u16,         // Initial (relative) CS value
63    e_lfarlc: u16,     // File address of relocation table
64    e_ovno: u16,       // Overlay number
65    e_res: [u16; 4],   // Reserved words
66    e_oemid: u16,      // OEM identifier (for e_oeminfo)
67    e_oeminfo: u16,    // OEM information; e_oemid specific
68    e_res2: [u16; 10], // Reserved words
69    e_lfanew: i32,     // File address of new exe header
70}
71
72#[repr(C)]
73#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
74struct TeImageHeader {
75    signature: u16,
76    machine: u16,
77    number_of_sections: u8,
78    subsystem: u8,
79    stripped_size: u16,
80    address_of_entry_point: u32,
81    base_of_code: u32,
82    image_base: u64,
83    data_directory: [ImageDataDirectory; 2],
84}
85
86#[repr(C)]
87#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
88struct ImageNtHeaders32 {
89    signature: u32,
90    file_header: ImageFileHeader,
91    optional_header: ImageOptionalHeader32,
92}
93
94#[repr(C)]
95#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
96struct ImageFileHeader {
97    machine: u16,
98    number_of_sections: u16,
99    time_date_stamp: u32,
100    pointer_to_symbol_table: u32,
101    number_of_symbols: u32,
102    size_of_optional_header: u16,
103    characteristics: u16,
104}
105
106#[repr(C)]
107#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
108struct ImageOptionalHeader32 {
109    magic: u16,
110    major_linker_version: u8,
111    minor_linker_version: u8,
112    size_of_code: u32,
113    size_of_initialized_data: u32,
114    size_of_uninitialized_data: u32,
115    address_of_entry_point: u32,
116    base_of_code: u32,
117    base_of_data: u32,
118    image_base: u32,
119    section_alignment: u32,
120    file_alignment: u32,
121    major_operating_system_version: u16,
122    minor_operating_system_version: u16,
123    major_image_version: u16,
124    minor_image_version: u16,
125    major_subsystem_version: u16,
126    minor_subsystem_version: u16,
127    win32_version_value: u32,
128    size_of_image: u32,
129    size_of_headers: u32,
130    check_sum: u32,
131    subsystem: u16,
132    dll_characteristics: u16,
133    size_of_stack_reserve: u32,
134    size_of_stack_commit: u32,
135    size_of_heap_reserve: u32,
136    size_of_heap_commit: u32,
137    loader_flags: u32,
138    number_of_rva_and_sizes: u32,
139    data_directory: [ImageDataDirectory; 16],
140}
141
142#[repr(C)]
143#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
144struct ImageDataDirectory {
145    virtual_address: u32,
146    size: u32,
147}
148
149fn pe_get_entry_point_offset(pe32_data: &[u8]) -> Option<u32> {
150    let dos_header = ImageDosHeader::read_from_prefix(pe32_data).ok()?.0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
151    let nt_headers_offset = if dos_header.e_magic == IMAGE_DOS_SIGNATURE {
152        // DOS image header is present, so read the PE header after the DOS image header.
153        dos_header.e_lfanew as usize
154    } else {
155        // DOS image header is not present, so PE header is at the image base.
156        0
157    };
158
159    let signature = u32::read_from_prefix(&pe32_data[nt_headers_offset..])
160        .ok()?
161        .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
162
163    // Calculate the entry point relative to the start of the image.
164    // AddressOfEntryPoint is common for PE32 & PE32+
165    if signature as u16 == TE_IMAGE_HEADER_SIGNATURE {
166        let te = TeImageHeader::read_from_prefix(&pe32_data[nt_headers_offset..])
167            .ok()?
168            .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
169        Some(te.address_of_entry_point + size_of_val(&te) as u32 - te.stripped_size as u32)
170    } else if signature == IMAGE_NT_SIGNATURE {
171        let pe = ImageNtHeaders32::read_from_prefix(&pe32_data[nt_headers_offset..])
172            .ok()?
173            .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
174        Some(pe.optional_header.address_of_entry_point)
175    } else {
176        None
177    }
178}
179
180#[repr(C)]
181#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
182struct EFI_FIRMWARE_VOLUME_HEADER {
183    zero_vector: [u8; 16],
184    file_system_guid: Guid,
185    fv_length: u64,
186    signature: u32,
187    attributes: u32,
188    header_length: u16,
189    checksum: u16,
190    ext_header_offset: u16,
191    reserved: u8,
192    revision: u8,
193}
194
195#[repr(C)]
196#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
197struct EFI_FFS_FILE_HEADER {
198    name: Guid,
199    integrity_check: u16,
200    typ: u8,
201    attributes: u8,
202    size: [u8; 3],
203    state: u8,
204}
205
206const EFI_FV_FILETYPE_SECURITY_CORE: u8 = 3;
207
208#[repr(C)]
209#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
210struct EFI_COMMON_SECTION_HEADER {
211    size: [u8; 3],
212    typ: u8,
213}
214
215const EFI_SECTION_PE32: u8 = 0x10;
216
217/// Get the SEC entry point offset from the firmware base.
218fn get_sec_entry_point_offset(image: &[u8]) -> Option<u64> {
219    // Skip to SEC volume start.
220    let mut image_offset = SEC_FIRMWARE_VOLUME_OFFSET;
221
222    // Expect a firmware volume header for SEC volume.
223    let fvh = EFI_FIRMWARE_VOLUME_HEADER::read_from_prefix(&image[image_offset as usize..])
224        .ok()?
225        .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
226    if fvh.signature != EFI_FVH_SIGNATURE {
227        return None;
228    }
229
230    // Skip past firmware volume header to beginning of firmware volume.
231    image_offset += fvh.header_length as u64;
232
233    // Find the first SEC CORE file type.
234    let mut sec_core_file_header = None;
235    let mut volume_offset = 0;
236    while volume_offset < fvh.fv_length {
237        let new_volume_offset = (volume_offset + 7) & !7;
238        if new_volume_offset > volume_offset {
239            image_offset += new_volume_offset - volume_offset;
240            volume_offset = new_volume_offset;
241        }
242        let fh = EFI_FFS_FILE_HEADER::read_from_prefix(&image[image_offset as usize..])
243            .ok()?
244            .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
245        if fh.typ == EFI_FV_FILETYPE_SECURITY_CORE {
246            sec_core_file_header = Some(fh);
247            break;
248        }
249
250        image_offset += expand_3byte_integer(fh.size);
251        volume_offset += expand_3byte_integer(fh.size);
252    }
253
254    // There should always be a Security Core file.
255    let sec_core_file_header = sec_core_file_header?;
256    let sec_core_file_size = expand_3byte_integer(sec_core_file_header.size);
257
258    // Move past the firmware file header.
259    image_offset += size_of::<EFI_FFS_FILE_HEADER>() as u64;
260    volume_offset += size_of::<EFI_FFS_FILE_HEADER>() as u64;
261
262    // Loop through the firmware file sections looking for PE section.
263    let mut file_offset = volume_offset;
264    while file_offset < sec_core_file_size {
265        //
266        // Section headers are 8 byte aligned with respect to the beginning of the file stream.
267        //
268        let new_file_offset = (file_offset + 3) & !3;
269        if new_file_offset > file_offset {
270            image_offset += new_file_offset - file_offset;
271            file_offset += new_file_offset - file_offset;
272        }
273
274        let sh = EFI_COMMON_SECTION_HEADER::read_from_prefix(&image[image_offset as usize..])
275            .ok()?
276            .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
277        if sh.typ == EFI_SECTION_PE32 {
278            let pe_offset = pe_get_entry_point_offset(
279                &image[image_offset as usize + size_of::<EFI_COMMON_SECTION_HEADER>()..],
280            )?;
281            image_offset += size_of::<EFI_COMMON_SECTION_HEADER>() as u64 + pe_offset as u64;
282            break;
283        }
284        image_offset += expand_3byte_integer(sh.size);
285        file_offset += expand_3byte_integer(sh.size);
286    }
287
288    Some(image_offset)
289}
290
291/// Definitions shared by UEFI and the loader when loaded with parameters passed in IGVM format.
292mod igvm {
293    use zerocopy::FromBytes;
294
295    use zerocopy::Immutable;
296    use zerocopy::IntoBytes;
297    use zerocopy::KnownLayout;
298
299    /// The structure used to tell UEFI where the IGVM loaded parameters are.
300    #[repr(C)]
301    #[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
302    pub struct UEFI_IGVM_PARAMETER_INFO {
303        pub parameter_page_count: u32,
304        pub cpuid_pages_offset: u32,
305        pub vp_context_page_number: u64,
306        pub loader_block_offset: u32,
307        pub command_line_offset: u32,
308        pub command_line_page_count: u32,
309        pub memory_map_offset: u32,
310        pub memory_map_page_count: u32,
311        pub madt_offset: u32,
312        pub madt_page_count: u32,
313        pub srat_offset: u32,
314        pub srat_page_count: u32,
315        pub maximum_processor_count: u32,
316        pub uefi_memory_map_offset: u32,
317        pub uefi_memory_map_page_count: u32,
318    }
319
320    pub const UEFI_IGVM_LOADER_BLOCK_NUMBER_OF_PROCESSORS_FIELD_OFFSET: usize = 0;
321}
322
323#[derive(Debug, Error)]
324pub enum Error {
325    #[error("Firmware size invalid")]
326    InvalidImageSize,
327    #[error("Unable to find SEC volume entry point")]
328    NoSecEntryPoint,
329    #[error("Invalid shared gpa boundary")]
330    InvalidSharedGpaBoundary,
331    #[error("Invalid config type")]
332    InvalidConfigType(String),
333    #[error("Importer error")]
334    Importer(#[source] anyhow::Error),
335    #[error("PageTableBuilder: {0}")]
336    PageTableBuilder(#[from] page_table::Error),
337}
338
339#[derive(Debug)]
340pub enum ConfigType {
341    ConfigBlob(config::Blob),
342    Igvm,
343    None,
344}
345
346#[derive(Debug)]
347pub struct LoadInfo {
348    /// The GPA the firmware was loaded at.
349    pub firmware_base: u64,
350    /// The size of the firmware image loaded, in bytes.
351    pub firmware_size: u64,
352    /// The total size used by the loader starting at the firmware_base,
353    /// including the firmware image and misc data, in bytes.
354    pub total_size: u64,
355}
356
357pub mod x86_64 {
358    use super::ConfigType;
359    use super::Error;
360    use super::LoadInfo;
361    use crate::common::DEFAULT_GDT_SIZE;
362    use crate::common::import_default_gdt;
363    use crate::cpuid::HV_PSP_CPUID_PAGE;
364    use crate::importer::BootPageAcceptance;
365    use crate::importer::IgvmParameterType;
366    use crate::importer::ImageLoad;
367    use crate::importer::IsolationType;
368    use crate::importer::StartupMemoryType;
369    use crate::importer::X86Register;
370    use crate::uefi::SEC_FIRMWARE_VOLUME_OFFSET;
371    use crate::uefi::get_sec_entry_point_offset;
372    use hvdef::HV_PAGE_SIZE;
373    use page_table::IdentityMapSize;
374    use page_table::x64::IdentityMapBuilder;
375    use page_table::x64::PAGE_TABLE_MAX_BYTES;
376    use page_table::x64::PAGE_TABLE_MAX_COUNT;
377    use page_table::x64::PageTable;
378    use page_table::x64::align_up_to_page_size;
379    use zerocopy::FromZeros;
380    use zerocopy::IntoBytes;
381
382    pub const IMAGE_SIZE: u64 = 0x00600000; // 6 MB. See MsvmPkg\MsvmPkgX64.fdf
383    const IMAGE_GPA_BASE: u64 = 0x100000; // 1MB
384    const PAGE_TABLE_GPA_BASE: u64 = IMAGE_GPA_BASE + IMAGE_SIZE; // 7MB - 0x700000
385    const PAGE_TABLE_SIZE: u64 = HV_PAGE_SIZE * 6;
386    const GDT_GPA_BASE: u64 = PAGE_TABLE_GPA_BASE + PAGE_TABLE_SIZE; // 0x707000
387    const MISC_PAGES_GPA_BASE: u64 = GDT_GPA_BASE + DEFAULT_GDT_SIZE; // 0x707000
388    const MISC_PAGES_SIZE: u64 = HV_PAGE_SIZE * 2;
389    pub const CONFIG_BLOB_GPA_BASE: u64 = MISC_PAGES_GPA_BASE + MISC_PAGES_SIZE; // 0x709000
390
391    /// Load a UEFI image with the provided config type.
392    pub fn load(
393        importer: &mut dyn ImageLoad<X86Register>,
394        image: &[u8],
395        config: ConfigType,
396    ) -> Result<LoadInfo, Error> {
397        if image.len() != IMAGE_SIZE as usize {
398            return Err(Error::InvalidImageSize);
399        }
400
401        let sec_entry_point = get_sec_entry_point_offset(image).ok_or(Error::NoSecEntryPoint)?;
402
403        let isolation = importer.isolation_config();
404
405        // Build the page tables. This depends on if we have a paravisor present or not:
406        //      - If this is an SNP VM with no paravisor, then build a set of page tables
407        //        to map the bottom 4GB of memory with shared visibility.
408        //      - Otherwise, build the standard UEFI page tables. Bottom 4GB of address space,
409        //        identity mapped with 2 MB pages.
410        let mut page_table_work_buffer: Vec<PageTable> =
411            vec![PageTable::new_zeroed(); PAGE_TABLE_MAX_COUNT];
412        let mut page_tables: Vec<u8> = vec![0; PAGE_TABLE_MAX_BYTES];
413        let page_table_builder = IdentityMapBuilder::new(
414            PAGE_TABLE_GPA_BASE,
415            IdentityMapSize::Size4Gb,
416            page_table_work_buffer.as_mut_slice(),
417            page_tables.as_mut_slice(),
418        )?;
419        let mut shared_vis_page_table_work_buffer: Vec<PageTable> = Vec::new();
420        let mut shared_vis_page_tables: Vec<u8> = Vec::new();
421        let (page_tables, shared_vis_page_tables) =
422            if isolation.isolation_type == IsolationType::Snp && !isolation.paravisor_present {
423                if let ConfigType::ConfigBlob(_) = config {
424                    return Err(Error::InvalidConfigType(
425                        "Enlightened UEFI must use IGVM parameters".into(),
426                    ));
427                }
428
429                let shared_vis_page_table_gpa = CONFIG_BLOB_GPA_BASE + HV_PAGE_SIZE;
430                let shared_gpa_boundary_bits = isolation
431                    .shared_gpa_boundary_bits
432                    .ok_or(Error::InvalidSharedGpaBoundary)?;
433                let shared_gpa_boundary = 1 << shared_gpa_boundary_bits;
434
435                shared_vis_page_table_work_buffer
436                    .resize(PAGE_TABLE_MAX_COUNT, PageTable::new_zeroed());
437                shared_vis_page_tables.resize(PAGE_TABLE_MAX_BYTES, 0);
438                let shared_vis_builder = IdentityMapBuilder::new(
439                    shared_vis_page_table_gpa,
440                    IdentityMapSize::Size4Gb,
441                    shared_vis_page_table_work_buffer.as_mut_slice(),
442                    shared_vis_page_tables.as_mut_slice(),
443                )?
444                .with_address_bias(shared_gpa_boundary);
445
446                // The extra page tables are placed after the first config blob
447                // page.  They will be accounted for when the IGVM parameters are
448                // built.
449                let shared_vis_page_tables = shared_vis_builder.build();
450
451                let page_tables = page_table_builder
452                    .with_pml4e_link((shared_vis_page_table_gpa, shared_gpa_boundary))
453                    .build();
454
455                (page_tables, Some(shared_vis_page_tables))
456            } else {
457                let page_tables = page_table_builder.build();
458                (page_tables, None)
459            };
460
461        // Size must match expected compiled constant
462        assert_eq!(page_tables.len(), PAGE_TABLE_SIZE as usize);
463
464        // Import image, page tables, GDT entries.
465        let image_page_count = image.len() as u64 / HV_PAGE_SIZE;
466        importer
467            .import_pages(
468                IMAGE_GPA_BASE / HV_PAGE_SIZE,
469                image_page_count,
470                "uefi-image",
471                BootPageAcceptance::Exclusive,
472                image,
473            )
474            .map_err(Error::Importer)?;
475
476        let mut total_page_count = IMAGE_GPA_BASE / HV_PAGE_SIZE + image_page_count;
477
478        importer
479            .import_pages(
480                PAGE_TABLE_GPA_BASE / HV_PAGE_SIZE,
481                PAGE_TABLE_SIZE / HV_PAGE_SIZE,
482                "uefi-page-tables",
483                BootPageAcceptance::Exclusive,
484                page_tables,
485            )
486            .map_err(Error::Importer)?;
487
488        total_page_count += PAGE_TABLE_SIZE / HV_PAGE_SIZE;
489
490        // The default GDT is used with a page count of one.
491        assert_eq!(DEFAULT_GDT_SIZE, HV_PAGE_SIZE);
492        import_default_gdt(importer, GDT_GPA_BASE / HV_PAGE_SIZE).map_err(Error::Importer)?;
493        total_page_count += DEFAULT_GDT_SIZE / HV_PAGE_SIZE;
494
495        // Reserve free pages. Currently these are only used by UEFI PEI for making hypercalls.
496        importer
497            .import_pages(
498                MISC_PAGES_GPA_BASE / HV_PAGE_SIZE,
499                MISC_PAGES_SIZE / HV_PAGE_SIZE,
500                "uefi-misc-pages",
501                BootPageAcceptance::Exclusive,
502                &[],
503            )
504            .map_err(Error::Importer)?;
505
506        total_page_count += MISC_PAGES_SIZE / HV_PAGE_SIZE;
507
508        // Import the config blobg, if set. Some callers may not load UEFI
509        // configuration at this time, such as if running with a paravisor.
510        match config {
511            ConfigType::Igvm => {
512                total_page_count += set_igvm_parameters(
513                    importer,
514                    CONFIG_BLOB_GPA_BASE / HV_PAGE_SIZE,
515                    match isolation.isolation_type {
516                        IsolationType::Snp => shared_vis_page_tables
517                            .as_ref()
518                            .expect("should be shared vis page tables"),
519                        _ => &[],
520                    },
521                )?
522            }
523            ConfigType::ConfigBlob(config) => {
524                let data = config.complete();
525                assert!(!data.is_empty());
526                let config_blob_page_count = (data.len() as u64).div_ceil(HV_PAGE_SIZE);
527                importer
528                    .import_pages(
529                        CONFIG_BLOB_GPA_BASE / HV_PAGE_SIZE,
530                        config_blob_page_count,
531                        "uefi-config-blob",
532                        BootPageAcceptance::Exclusive,
533                        &data,
534                    )
535                    .map_err(Error::Importer)?;
536
537                total_page_count += config_blob_page_count;
538            }
539            ConfigType::None => {}
540        }
541
542        // UEFI expects that the memory from GPA 0 up until the end of the config
543        // blob is present, at a minimum. Note that ImageGpaBase is not 0.
544        importer
545            .verify_startup_memory_available(0, total_page_count, StartupMemoryType::Ram)
546            .map_err(Error::Importer)?;
547
548        let mut import_reg = |register| {
549            importer
550                .import_vp_register(register)
551                .map_err(Error::Importer)
552        };
553
554        // Set CR0
555        import_reg(X86Register::Cr0(
556            x86defs::X64_CR0_PG | x86defs::X64_CR0_NE | x86defs::X64_CR0_MP | x86defs::X64_CR0_PE,
557        ))?;
558
559        // Set CR3 to point to page table which starts right after the image.
560        import_reg(X86Register::Cr3(PAGE_TABLE_GPA_BASE))?;
561
562        // Set CR4
563        import_reg(X86Register::Cr4(
564            x86defs::X64_CR4_PAE
565                | x86defs::X64_CR4_MCE
566                | x86defs::X64_CR4_FXSR
567                | x86defs::X64_CR4_XMMEXCPT,
568        ))?;
569
570        // Set EFER to LME, LMA, and NXE for 64 bit mode.
571        import_reg(X86Register::Efer(
572            x86defs::X64_EFER_LMA | x86defs::X64_EFER_LME | x86defs::X64_EFER_NXE,
573        ))?;
574
575        // Set PAT
576        import_reg(X86Register::Pat(x86defs::X86X_MSR_DEFAULT_PAT))?;
577
578        // Set register state to values SEC entry point expects.
579        // RBP - start of BFV (sec FV)
580        import_reg(X86Register::Rbp(
581            IMAGE_GPA_BASE + SEC_FIRMWARE_VOLUME_OFFSET,
582        ))?;
583
584        // Set RIP to SEC entry point.
585        import_reg(X86Register::Rip(IMAGE_GPA_BASE + sec_entry_point))?;
586
587        // Set R8-R11 to the hypervisor isolation CPUID leaf values.
588        let isolation_cpuid = isolation.get_cpuid();
589
590        import_reg(X86Register::R8(isolation_cpuid.eax as u64))?;
591        import_reg(X86Register::R9(isolation_cpuid.ebx as u64))?;
592        import_reg(X86Register::R10(isolation_cpuid.ecx as u64))?;
593        import_reg(X86Register::R11(isolation_cpuid.edx as u64))?;
594
595        // Enable MTRRs, default MTRR is uncached, and set lowest 640KB as WB
596        import_reg(X86Register::MtrrDefType(0xc00))?;
597        import_reg(X86Register::MtrrFix64k00000(0x0606060606060606))?;
598        import_reg(X86Register::MtrrFix16k80000(0x0606060606060606))?;
599
600        Ok(LoadInfo {
601            firmware_base: IMAGE_GPA_BASE,
602            firmware_size: image.len() as u64,
603            total_size: total_page_count * HV_PAGE_SIZE,
604        })
605    }
606
607    /// A simple page allocator that supports allocating pages counting up from a base page.
608    struct PageAllocator {
609        base: u32,
610        total_count: u32,
611    }
612
613    impl PageAllocator {
614        /// Create a `PageAllocator` starting at the given page `base`.
615        fn new(base: u32) -> PageAllocator {
616            PageAllocator {
617                base,
618                total_count: 0,
619            }
620        }
621
622        /// Allocate `count` number of pages. Returns the base page number for the allocation.
623        fn allocate(&mut self, count: u32) -> u32 {
624            let allocation = self.base + self.total_count;
625            self.total_count += count;
626
627            allocation
628        }
629
630        /// Get the total number of pages allocated.
631        fn total(&self) -> u32 {
632            self.total_count
633        }
634    }
635
636    /// Construct the UEFI parameter information in IGVM format. `config_area_base_page` specifies the GPA page number
637    /// at the start of the config region. The number of pages used in the config region is returned.
638    fn set_igvm_parameters(
639        importer: &mut dyn ImageLoad<X86Register>,
640        config_area_base_page: u64,
641        shared_visibility_page_tables: &[u8],
642    ) -> Result<u64, Error> {
643        let mut parameter_info = super::igvm::UEFI_IGVM_PARAMETER_INFO::new_zeroed();
644
645        // IGVM UEFI_IGVM_PARAMETER_INFO page offsets are relative to 1, as the first page is taken by the
646        // UEFI_IGVM_PARAMETER_INFO structure. Allocate a page for the UEFI_IGVM_PARAMETER_INFO structure.
647        let mut allocator = PageAllocator::new(0);
648        allocator.allocate(1);
649
650        // Set up the parameter info structure with offsets to each of the
651        // additional parameters. Each table allocates a constant number of
652        // pages.
653        let table_page_count = 20;
654
655        // The first structure is the loader block, which happens after the parameter info structure and shared
656        // visibility page tables.
657        let page_table_page_count =
658            align_up_to_page_size(shared_visibility_page_tables.len() as u64) / HV_PAGE_SIZE;
659        let page_table_offset = allocator.allocate(page_table_page_count as u32);
660        parameter_info.loader_block_offset = allocator.allocate(1);
661
662        let command_line_page_count = 1;
663        parameter_info.command_line_offset = allocator.allocate(command_line_page_count);
664        parameter_info.command_line_page_count = command_line_page_count;
665
666        parameter_info.memory_map_offset = allocator.allocate(table_page_count);
667        parameter_info.memory_map_page_count = table_page_count;
668
669        parameter_info.madt_offset = allocator.allocate(table_page_count);
670        parameter_info.madt_page_count = table_page_count;
671
672        parameter_info.srat_offset = allocator.allocate(table_page_count);
673        parameter_info.srat_page_count = table_page_count;
674
675        // Reserve additional pre-accepted pages for UEFI to use to reconstruct
676        // portions of the config blob.
677        parameter_info.uefi_memory_map_offset = allocator.allocate(table_page_count);
678        parameter_info.uefi_memory_map_page_count = table_page_count;
679
680        // If this is an SNP image with no paravisor, then reserve additional pages as required.
681        let isolation = importer.isolation_config();
682        if isolation.isolation_type == IsolationType::Snp {
683            // NOTE: Currently UEFI expects this parameter load style to have no paravisor. Disallow that here.
684            if isolation.paravisor_present {
685                return Err(Error::InvalidConfigType(
686                    "IGVM ConfigType specified but paravisor is present.".into(),
687                ));
688            }
689
690            // Supply the address of the parameter info block so it can be used
691            // before PEI parses the config information.
692            importer
693                .import_vp_register(X86Register::R12(config_area_base_page * HV_PAGE_SIZE))
694                .map_err(Error::Importer)?;
695
696            // Reserve two pages to hold CPUID information. The first CPUID page
697            // contains initialized data to query CPUID leaves. The second page
698            // contains no data, as it will be populated by the host when the
699            // image is loaded.
700            parameter_info.cpuid_pages_offset = allocator.allocate(2);
701
702            let cpuid_page = create_snp_cpuid_page();
703
704            importer
705                .import_pages(
706                    config_area_base_page + parameter_info.cpuid_pages_offset as u64,
707                    1,
708                    "uefi-cpuid-page",
709                    BootPageAcceptance::CpuidPage,
710                    cpuid_page.as_bytes(),
711                )
712                .map_err(Error::Importer)?;
713
714            importer
715                .import_pages(
716                    config_area_base_page + parameter_info.cpuid_pages_offset as u64 + 1,
717                    1,
718                    "uefi-cpuid-extended-page",
719                    BootPageAcceptance::CpuidExtendedStatePage,
720                    &[],
721                )
722                .map_err(Error::Importer)?;
723
724            // Reserve a page to use to hold the VMSA.  This must be reported to
725            // UEFI so that the page can be marked as a permanent firmware
726            // allocation.
727            //
728            // Note that this page must not be counted within the size of the
729            // config block, since it has different memory protection properties.
730            // The first page following the config block is chosen for the
731            // allocation.
732            let vp_context_page_number = config_area_base_page + allocator.total() as u64;
733            importer
734                .set_vp_context_page(vp_context_page_number)
735                .map_err(Error::Importer)?;
736
737            parameter_info.vp_context_page_number = vp_context_page_number;
738        } else {
739            // If this is not an SNP image, then the VP context page does not
740            // need to be reported to UEFI. Put in the TDX reset page value for
741            // consistency with old code; this probably is unnecessary (or the
742            // UEFI firmware should just be improved to not need this).
743            parameter_info.vp_context_page_number = 0xfffff;
744        }
745
746        // Encode the total amount of pages used by all parameters.
747        parameter_info.parameter_page_count = allocator.total();
748
749        importer
750            .import_pages(
751                config_area_base_page,
752                1,
753                "uefi-config-base-page",
754                BootPageAcceptance::Exclusive,
755                parameter_info.as_bytes(),
756            )
757            .map_err(Error::Importer)?;
758
759        importer
760            .import_pages(
761                config_area_base_page + parameter_info.uefi_memory_map_offset as u64,
762                parameter_info.uefi_memory_map_page_count as u64,
763                "uefi-memory-map-scratch",
764                BootPageAcceptance::ExclusiveUnmeasured,
765                &[],
766            )
767            .map_err(Error::Importer)?;
768
769        let loader_block = importer
770            .create_parameter_area(
771                config_area_base_page + parameter_info.loader_block_offset as u64,
772                1,
773                "uefi-loader-block",
774            )
775            .map_err(Error::Importer)?;
776        importer
777            .import_parameter(
778                loader_block,
779                super::igvm::UEFI_IGVM_LOADER_BLOCK_NUMBER_OF_PROCESSORS_FIELD_OFFSET as u32,
780                IgvmParameterType::VpCount,
781            )
782            .map_err(Error::Importer)?;
783
784        let command_line = importer
785            .create_parameter_area(
786                config_area_base_page + parameter_info.command_line_offset as u64,
787                parameter_info.command_line_page_count,
788                "uefi-command-line",
789            )
790            .map_err(Error::Importer)?;
791        importer
792            .import_parameter(command_line, 0, IgvmParameterType::CommandLine)
793            .map_err(Error::Importer)?;
794
795        let memory_map = importer
796            .create_parameter_area(
797                config_area_base_page + parameter_info.memory_map_offset as u64,
798                parameter_info.memory_map_page_count,
799                "uefi-memory-map",
800            )
801            .map_err(Error::Importer)?;
802        importer
803            .import_parameter(memory_map, 0, IgvmParameterType::MemoryMap)
804            .map_err(Error::Importer)?;
805
806        let madt = importer
807            .create_parameter_area(
808                config_area_base_page + parameter_info.madt_offset as u64,
809                parameter_info.madt_page_count,
810                "uefi-madt",
811            )
812            .map_err(Error::Importer)?;
813        importer
814            .import_parameter(madt, 0, IgvmParameterType::Madt)
815            .map_err(Error::Importer)?;
816
817        let srat = importer
818            .create_parameter_area(
819                config_area_base_page + parameter_info.srat_offset as u64,
820                parameter_info.srat_page_count,
821                "uefi-srat",
822            )
823            .map_err(Error::Importer)?;
824        importer
825            .import_parameter(srat, 0, IgvmParameterType::Srat)
826            .map_err(Error::Importer)?;
827
828        if page_table_page_count != 0 {
829            importer
830                .import_pages(
831                    config_area_base_page + page_table_offset as u64,
832                    page_table_page_count,
833                    "uefi-igvm-page-tables",
834                    BootPageAcceptance::Exclusive,
835                    shared_visibility_page_tables,
836                )
837                .map_err(Error::Importer)?;
838        }
839
840        Ok(allocator.total() as u64)
841    }
842
843    /// Create a hypervisor SNP CPUID page with the default values.
844    fn create_snp_cpuid_page() -> HV_PSP_CPUID_PAGE {
845        let mut cpuid_page = HV_PSP_CPUID_PAGE::default();
846
847        for (i, required_leaf) in crate::cpuid::SNP_REQUIRED_CPUID_LEAF_LIST_UEFI
848            .iter()
849            .enumerate()
850        {
851            cpuid_page.cpuid_leaf_info[i].eax_in = required_leaf.eax;
852            cpuid_page.cpuid_leaf_info[i].eax_out = required_leaf.ecx;
853            cpuid_page.count += 1;
854        }
855
856        cpuid_page
857    }
858}
859
860pub mod aarch64 {
861    use super::ConfigType;
862    use super::Error;
863    use super::LoadInfo;
864    use crate::importer::Aarch64Register;
865    use crate::importer::BootPageAcceptance;
866    use crate::importer::ImageLoad;
867    use aarch64defs::Cpsr64;
868    use hvdef::HV_PAGE_SIZE;
869
870    use zerocopy::IntoBytes;
871
872    pub const IMAGE_SIZE: u64 = 0x800000;
873    pub const CONFIG_BLOB_GPA_BASE: u64 = 0x824000;
874
875    /// Load a UEFI image with the provided config type.
876    pub fn load(
877        importer: &mut dyn ImageLoad<Aarch64Register>,
878        image: &[u8],
879        config: ConfigType,
880    ) -> Result<LoadInfo, Error> {
881        if image.len() != IMAGE_SIZE as usize {
882            return Err(Error::InvalidImageSize);
883        }
884
885        const BYTES_2MB: u64 = 0x200000;
886
887        let image_size = (image.len() as u64 + BYTES_2MB - 1) & !(BYTES_2MB - 1);
888        importer
889            .import_pages(
890                0,
891                image_size / HV_PAGE_SIZE,
892                "uefi-image",
893                BootPageAcceptance::Exclusive,
894                image,
895            )
896            .map_err(Error::Importer)?;
897
898        // The stack.
899        let stack_offset = image_size;
900        let stack_size = 32 * HV_PAGE_SIZE;
901        let stack_end = stack_offset + stack_size;
902        importer
903            .import_pages(
904                stack_offset / HV_PAGE_SIZE,
905                stack_size / HV_PAGE_SIZE,
906                "uefi-stack",
907                BootPageAcceptance::Exclusive,
908                &[],
909            )
910            .map_err(Error::Importer)?;
911
912        // The page tables.
913        let page_table_offset = stack_end;
914        let page_tables = page_tables(page_table_offset, 1 << 30 /* TODO */);
915        importer
916            .import_pages(
917                page_table_offset / HV_PAGE_SIZE,
918                page_tables.as_bytes().len() as u64 / HV_PAGE_SIZE,
919                "uefi-page-tables",
920                BootPageAcceptance::Exclusive,
921                page_tables.as_bytes(),
922            )
923            .map_err(Error::Importer)?;
924
925        let blob_offset = CONFIG_BLOB_GPA_BASE;
926
927        // The config blob.
928        let blob_size = match config {
929            ConfigType::ConfigBlob(blob) => {
930                let blob = blob.complete();
931                let blob_size = (blob.len() as u64 + HV_PAGE_SIZE - 1) & !(HV_PAGE_SIZE - 1);
932                importer
933                    .import_pages(
934                        blob_offset / HV_PAGE_SIZE,
935                        blob_size / HV_PAGE_SIZE,
936                        "uefi-config-blob",
937                        BootPageAcceptance::Exclusive,
938                        &blob,
939                    )
940                    .map_err(Error::Importer)?;
941
942                blob_size
943            }
944            ConfigType::None => 0,
945            ConfigType::Igvm => {
946                return Err(Error::InvalidConfigType("igvm not supported".to_owned()));
947            }
948        };
949
950        let total_size = blob_offset + blob_size;
951
952        let mut import_reg = |reg| importer.import_vp_register(reg).map_err(Error::Importer);
953
954        import_reg(Aarch64Register::Cpsr(
955            Cpsr64::new().with_sp(true).with_el(1).into(),
956        ))?;
957        import_reg(Aarch64Register::X0(0x1000))?;
958        import_reg(Aarch64Register::Pc(0x1000))?;
959        import_reg(Aarch64Register::X1(stack_end))?;
960
961        import_reg(Aarch64Register::Ttbr0El1(page_table_offset))?;
962
963        // Memory attribute indirection register.
964        const ARM64_MAIR_CACHE_WBWA: u64 = 0xff;
965        const ARM64_MAIR_CACHE_NC: u64 = 0x00;
966        const ARM64_MAIR_CACHE_WTNA: u64 = 0xaa;
967        const ARM64_MAIR_CACHE_WC: u64 = 0x44;
968
969        import_reg(Aarch64Register::MairEl1(
970            ARM64_MAIR_CACHE_WBWA
971                | (ARM64_MAIR_CACHE_NC << 8)
972                | (ARM64_MAIR_CACHE_WTNA << 16)
973                | (ARM64_MAIR_CACHE_WC << 24)
974                | (ARM64_MAIR_CACHE_WBWA << 32)
975                | (ARM64_MAIR_CACHE_NC << 40)
976                | (ARM64_MAIR_CACHE_WTNA << 48)
977                | (ARM64_MAIR_CACHE_WC << 56),
978        ))?;
979
980        // System control register.
981        const ARM64_SCTLR_M: u64 = 0x00000001;
982        const ARM64_SCTLR_C: u64 = 0x00000004;
983        const ARM64_SCTLR_RES1_11: u64 = 0x00000800;
984        const ARM64_SCTLR_I: u64 = 0x00001000;
985        const ARM64_SCTLR_RES1_20: u64 = 0x00100000;
986        const ARM64_SCTLR_RES1_22: u64 = 0x00400000;
987        const ARM64_SCTLR_RES1_23: u64 = 0x00800000;
988        const ARM64_SCTLR_RES1_28: u64 = 0x10000000;
989        const ARM64_SCTLR_RES1_29: u64 = 0x20000000;
990
991        import_reg(Aarch64Register::SctlrEl1(
992            ARM64_SCTLR_M
993                | ARM64_SCTLR_C
994                | ARM64_SCTLR_I
995                | ARM64_SCTLR_RES1_11
996                | ARM64_SCTLR_RES1_20
997                | ARM64_SCTLR_RES1_22
998                | ARM64_SCTLR_RES1_23
999                | ARM64_SCTLR_RES1_28
1000                | ARM64_SCTLR_RES1_29,
1001        ))?;
1002
1003        // Translation control register.
1004
1005        const ARM64_TCR_IRGN0_WBWA: u64 = 0x0000000000000100;
1006        const ARM64_TCR_ORGN0_WBWA: u64 = 0x0000000000000400;
1007        const ARM64_TCR_SH0_INNER_SHARED: u64 = 0x0000000000003000;
1008        const ARM64_TCR_TG0_4K: u64 = 0x0000000000000000;
1009        const ARM64_TCR_EPD1: u64 = 0x0000000000800000;
1010        const ARM64_TCR_T0SZ_SHIFT: u32 = 0;
1011        const ARM64_TCR_T1SZ_SHIFT: u32 = 16;
1012
1013        import_reg(Aarch64Register::TcrEl1(
1014            ARM64_TCR_EPD1
1015                | ARM64_TCR_TG0_4K
1016                | ARM64_TCR_SH0_INNER_SHARED
1017                | ARM64_TCR_ORGN0_WBWA
1018                | ARM64_TCR_IRGN0_WBWA
1019                | (16 << ARM64_TCR_T0SZ_SHIFT)
1020                | (16 << ARM64_TCR_T1SZ_SHIFT),
1021        ))?;
1022
1023        Ok(LoadInfo {
1024            firmware_base: 0,
1025            firmware_size: image.len() as u64,
1026            total_size,
1027        })
1028    }
1029
1030    const PTE_VALID: u64 = 1 << 0;
1031    const PTE_NOT_LARGE: u64 = 1 << 1;
1032    const PTE_MAIR_WB: u64 = 0 << 2;
1033    const PTE_MAIR_UC: u64 = 1 << 2;
1034    const PTE_SHARABILITY_INNER: u64 = 3 << 8;
1035    const PTE_ACCESSED: u64 = 1 << 10;
1036    const PTE_USER_NX: u64 = 1 << 54;
1037
1038    fn large_leaf_entry(normal: bool, address: u64) -> u64 {
1039        address
1040            | PTE_VALID
1041            | PTE_ACCESSED
1042            | PTE_SHARABILITY_INNER
1043            | PTE_USER_NX
1044            | if normal { PTE_MAIR_WB } else { PTE_MAIR_UC }
1045    }
1046
1047    fn non_leaf_entry(address: u64) -> u64 {
1048        address | PTE_VALID | PTE_NOT_LARGE
1049    }
1050
1051    fn leaf_entry(normal: bool, address: u64) -> u64 {
1052        address
1053            | PTE_VALID
1054            | PTE_ACCESSED
1055            | PTE_NOT_LARGE
1056            | PTE_SHARABILITY_INNER
1057            | PTE_USER_NX
1058            | if normal { PTE_MAIR_WB } else { PTE_MAIR_UC }
1059    }
1060
1061    fn table_index(va: u64, level: u32) -> usize {
1062        let index = va >> (9 * (3 - level) + 12);
1063        let index = index & ((1 << 9) - 1);
1064        index as usize
1065    }
1066
1067    fn page_tables(address: u64, end_of_ram: u64) -> Vec<[u64; 512]> {
1068        const PT_SIZE: u64 = 4096;
1069        const VA_4GB: u64 = 1 << 32;
1070        const VA_1GB: u64 = 1 << 30;
1071        const VA_2MB: u64 = 2 << 20;
1072        const VA_4KB: u64 = 4 << 10;
1073
1074        let mut buffer = vec![[0u64; PT_SIZE as usize / 8]; 4];
1075        let [level0, level1, level2, level3] = buffer.as_mut_slice() else {
1076            unreachable!()
1077        };
1078
1079        // Allocate temporary buffer to hold page tables. We need 4 page tables:
1080        // - PML4 table (level 0 table in ARM terminology).
1081        // - PDP table (level 1 table).
1082        // - PD table (level 2 table) to map the 1 GB region that contains the
1083        //   split between normal and device memory.
1084        // - PT table (level 3 table) to map the 2 MB region that contains the
1085        //   split between normal and device memory.
1086
1087        // Link level 1 translation table.
1088        level0[0] = non_leaf_entry(address + PT_SIZE);
1089
1090        // Create an identity map for the address space from 0 to 4 GB.
1091        // The range [0, 4GB - MMIO Space Size) is mapped as normal memory, the
1092        // range [4 GB - MMIO Space Size, 4 GB) is mapped as device memory.
1093
1094        let mut normal = true;
1095        let mut va = 0;
1096        let mut end_va = end_of_ram;
1097        while va < VA_4GB {
1098            //
1099            // Switch to device memory if we are are within the MMIO space.
1100            //
1101            if normal && va == end_va {
1102                normal = false;
1103                end_va = VA_4GB;
1104                continue;
1105            }
1106
1107            // Try to use a 1 GB page (level 1 block entry) if possible.
1108            let level1_index = table_index(va, 1);
1109            if level1[level1_index] & PTE_VALID == 0
1110                && ((va & (VA_1GB - 1)) == 0)
1111                && (end_va - va >= VA_1GB)
1112            {
1113                level1[level1_index] = large_leaf_entry(normal, va);
1114                va += VA_1GB;
1115                continue;
1116            }
1117
1118            //
1119            // Allocate and link level 2 translation table (PD) if it does not yet
1120            // exist.
1121            //
1122            if level1[level1_index] & PTE_VALID == 0 {
1123                level1[level1_index] = non_leaf_entry(address + PT_SIZE * 2);
1124            }
1125
1126            //
1127            // Try to use a 2 MB page (level 2 block entry) if possible.
1128            //
1129            let level2_index = table_index(va, 2);
1130            if level2[level2_index] & PTE_VALID == 0
1131                && ((va & (VA_2MB - 1)) == 0)
1132                && (end_va - va >= VA_2MB)
1133            {
1134                level2[level2_index] = large_leaf_entry(normal, va);
1135                va += VA_2MB;
1136                continue;
1137            }
1138
1139            //
1140            // Allocate and link level 1 translation table (PT) if it does not yet
1141            // exist.
1142            //
1143            if level2[level2_index] & PTE_VALID == 0 {
1144                level2[level2_index] = non_leaf_entry(address + PT_SIZE * 3);
1145            }
1146
1147            let level3_index = table_index(va, 3);
1148            level3[level3_index] = leaf_entry(normal, va);
1149            va += VA_4KB;
1150        }
1151
1152        buffer
1153    }
1154}
loader\uefi/mod.rs

loader\uefi/
mod.rs
