vmm_core/emuplat/
gic.rs

1// Copyright (c) Microsoft Corporation.
2// Licensed under the MIT License.
3
4//! Code to bridge between the `vmotherboard` interrupt controller and a `virt`
5//! partition GIC.
6
7use std::ops::RangeInclusive;
8use std::sync::Arc;
9use virt::irqcon::ControlGic;
10use vmcore::line_interrupt::LineSetTarget;
11
12/// Interrupt target for the GIC.
13///
14/// Maps the interrupt lines into GIC interrupt IDs. Only SPIs (starting at
15/// IRQ 32) are supported.
16pub struct GicInterruptTarget(Arc<dyn ControlGic>);
17
18impl GicInterruptTarget {
19    /// Returns a new [`LineSetTarget`].
20    pub fn new(irqcon: Arc<dyn ControlGic>) -> Self {
21        Self(irqcon)
22    }
23}
24
25pub const SPI_RANGE: RangeInclusive<u32> = 32..=1019;
26
27impl LineSetTarget for GicInterruptTarget {
28    fn set_irq(&self, vector: u32, high: bool) {
29        self.0.set_spi_irq(vector, high)
30    }
31}
vmm_core/emuplat/gic.rs

vmm_core/emuplat/
gic.rs
