loader/uefi/
mod.rs

1// Copyright (c) Microsoft Corporation.
2// Licensed under the MIT License.
3
4//! UEFI specific loader definitions and implementation.
5
6pub mod config;
7
8#[cfg(guest_arch = "aarch64")]
9use aarch64 as arch;
10#[cfg(guest_arch = "x86_64")]
11use x86_64 as arch;
12
13pub use arch::CONFIG_BLOB_GPA_BASE;
14pub use arch::IMAGE_SIZE;
15pub use arch::load;
16
17use guid::Guid;
18use thiserror::Error;
19use zerocopy::FromBytes;
20use zerocopy::Immutable;
21use zerocopy::IntoBytes;
22use zerocopy::KnownLayout;
23
24// Constant defining the offset within the image where the SEC volume starts.
25// TODO: Revisit this when we reorganize the firmware layout. One option
26// would be to just put the SEC volume at the start of the image, so no need
27// for this offset.
28const SEC_FIRMWARE_VOLUME_OFFSET: u64 = 0x005E0000;
29
30/// Expand a 3 byte sequence into little-endian integer.
31fn expand_3byte_integer(size: [u8; 3]) -> u64 {
32    ((size[2] as u64) << 16) + ((size[1] as u64) << 8) + size[0] as u64
33}
34
35const fn signature_16(v: &[u8; 2]) -> u16 {
36    v[0] as u16 | (v[1] as u16) << 8
37}
38
39const fn signature_32(v: &[u8; 4]) -> u32 {
40    v[0] as u32 | (v[1] as u32) << 8 | (v[2] as u32) << 16 | (v[3] as u32) << 24
41}
42
43const IMAGE_DOS_SIGNATURE: u16 = 0x5A4D; // MZ
44const IMAGE_NT_SIGNATURE: u32 = 0x00004550; // PE00
45const TE_IMAGE_HEADER_SIGNATURE: u16 = signature_16(b"VZ");
46const EFI_FVH_SIGNATURE: u32 = signature_32(b"_FVH");
47
48#[repr(C)]
49#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
50struct ImageDosHeader {
51    e_magic: u16,      // Magic number
52    e_cblp: u16,       // Bytes on last page of file
53    e_cp: u16,         // Pages in file
54    e_crlc: u16,       // Relocations
55    e_cparhdr: u16,    // Size of header in paragraphs
56    e_minalloc: u16,   // Minimum extra paragraphs needed
57    e_maxalloc: u16,   // Maximum extra paragraphs needed
58    e_ss: u16,         // Initial (relative) SS value
59    e_sp: u16,         // Initial SP value
60    e_csum: u16,       // Checksum
61    e_ip: u16,         // Initial IP value
62    e_cs: u16,         // Initial (relative) CS value
63    e_lfarlc: u16,     // File address of relocation table
64    e_ovno: u16,       // Overlay number
65    e_res: [u16; 4],   // Reserved words
66    e_oemid: u16,      // OEM identifier (for e_oeminfo)
67    e_oeminfo: u16,    // OEM information; e_oemid specific
68    e_res2: [u16; 10], // Reserved words
69    e_lfanew: i32,     // File address of new exe header
70}
71
72#[repr(C)]
73#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
74struct TeImageHeader {
75    signature: u16,
76    machine: u16,
77    number_of_sections: u8,
78    subsystem: u8,
79    stripped_size: u16,
80    address_of_entry_point: u32,
81    base_of_code: u32,
82    image_base: u64,
83    data_directory: [ImageDataDirectory; 2],
84}
85
86#[repr(C)]
87#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
88struct ImageNtHeaders32 {
89    signature: u32,
90    file_header: ImageFileHeader,
91    optional_header: ImageOptionalHeader32,
92}
93
94#[repr(C)]
95#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
96struct ImageFileHeader {
97    machine: u16,
98    number_of_sections: u16,
99    time_date_stamp: u32,
100    pointer_to_symbol_table: u32,
101    number_of_symbols: u32,
102    size_of_optional_header: u16,
103    characteristics: u16,
104}
105
106#[repr(C)]
107#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
108struct ImageOptionalHeader32 {
109    magic: u16,
110    major_linker_version: u8,
111    minor_linker_version: u8,
112    size_of_code: u32,
113    size_of_initialized_data: u32,
114    size_of_uninitialized_data: u32,
115    address_of_entry_point: u32,
116    base_of_code: u32,
117    base_of_data: u32,
118    image_base: u32,
119    section_alignment: u32,
120    file_alignment: u32,
121    major_operating_system_version: u16,
122    minor_operating_system_version: u16,
123    major_image_version: u16,
124    minor_image_version: u16,
125    major_subsystem_version: u16,
126    minor_subsystem_version: u16,
127    win32_version_value: u32,
128    size_of_image: u32,
129    size_of_headers: u32,
130    check_sum: u32,
131    subsystem: u16,
132    dll_characteristics: u16,
133    size_of_stack_reserve: u32,
134    size_of_stack_commit: u32,
135    size_of_heap_reserve: u32,
136    size_of_heap_commit: u32,
137    loader_flags: u32,
138    number_of_rva_and_sizes: u32,
139    data_directory: [ImageDataDirectory; 16],
140}
141
142#[repr(C)]
143#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
144struct ImageDataDirectory {
145    virtual_address: u32,
146    size: u32,
147}
148
149fn pe_get_entry_point_offset(pe32_data: &[u8]) -> Option<u32> {
150    let dos_header = ImageDosHeader::read_from_prefix(pe32_data).ok()?.0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
151    let nt_headers_offset = if dos_header.e_magic == IMAGE_DOS_SIGNATURE {
152        // DOS image header is present, so read the PE header after the DOS image header.
153        dos_header.e_lfanew as usize
154    } else {
155        // DOS image header is not present, so PE header is at the image base.
156        0
157    };
158
159    let signature = u32::read_from_prefix(&pe32_data[nt_headers_offset..])
160        .ok()?
161        .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
162
163    // Calculate the entry point relative to the start of the image.
164    // AddressOfEntryPoint is common for PE32 & PE32+
165    if signature as u16 == TE_IMAGE_HEADER_SIGNATURE {
166        let te = TeImageHeader::read_from_prefix(&pe32_data[nt_headers_offset..])
167            .ok()?
168            .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
169        Some(te.address_of_entry_point + size_of_val(&te) as u32 - te.stripped_size as u32)
170    } else if signature == IMAGE_NT_SIGNATURE {
171        let pe = ImageNtHeaders32::read_from_prefix(&pe32_data[nt_headers_offset..])
172            .ok()?
173            .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
174        Some(pe.optional_header.address_of_entry_point)
175    } else {
176        None
177    }
178}
179
180#[repr(C)]
181#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
182struct EFI_FIRMWARE_VOLUME_HEADER {
183    zero_vector: [u8; 16],
184    file_system_guid: Guid,
185    fv_length: u64,
186    signature: u32,
187    attributes: u32,
188    header_length: u16,
189    checksum: u16,
190    ext_header_offset: u16,
191    reserved: u8,
192    revision: u8,
193}
194
195#[repr(C)]
196#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
197struct EFI_FFS_FILE_HEADER {
198    name: Guid,
199    integrity_check: u16,
200    typ: u8,
201    attributes: u8,
202    size: [u8; 3],
203    state: u8,
204}
205
206const EFI_FV_FILETYPE_SECURITY_CORE: u8 = 3;
207
208#[repr(C)]
209#[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
210struct EFI_COMMON_SECTION_HEADER {
211    size: [u8; 3],
212    typ: u8,
213}
214
215const EFI_SECTION_PE32: u8 = 0x10;
216
217/// Get the SEC entry point offset from the firmware base.
218fn get_sec_entry_point_offset(image: &[u8]) -> Option<u64> {
219    // Skip to SEC volume start.
220    let mut image_offset = SEC_FIRMWARE_VOLUME_OFFSET;
221
222    // Expect a firmware volume header for SEC volume.
223    let fvh = EFI_FIRMWARE_VOLUME_HEADER::read_from_prefix(&image[image_offset as usize..])
224        .ok()?
225        .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
226    if fvh.signature != EFI_FVH_SIGNATURE {
227        return None;
228    }
229
230    // Skip past firmware volume header to beginning of firmware volume.
231    image_offset += fvh.header_length as u64;
232
233    // Find the first SEC CORE file type.
234    let mut sec_core_file_header = None;
235    let mut volume_offset = 0;
236    while volume_offset < fvh.fv_length {
237        let new_volume_offset = (volume_offset + 7) & !7;
238        if new_volume_offset > volume_offset {
239            image_offset += new_volume_offset - volume_offset;
240            volume_offset = new_volume_offset;
241        }
242        let fh = EFI_FFS_FILE_HEADER::read_from_prefix(&image[image_offset as usize..])
243            .ok()?
244            .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
245        if fh.typ == EFI_FV_FILETYPE_SECURITY_CORE {
246            sec_core_file_header = Some(fh);
247            break;
248        }
249
250        image_offset += expand_3byte_integer(fh.size);
251        volume_offset += expand_3byte_integer(fh.size);
252    }
253
254    // There should always be a Security Core file.
255    let sec_core_file_header = sec_core_file_header?;
256    let sec_core_file_size = expand_3byte_integer(sec_core_file_header.size);
257
258    // Move past the firmware file header.
259    image_offset += size_of::<EFI_FFS_FILE_HEADER>() as u64;
260    volume_offset += size_of::<EFI_FFS_FILE_HEADER>() as u64;
261
262    // Loop through the firmware file sections looking for PE section.
263    let mut file_offset = volume_offset;
264    while file_offset < sec_core_file_size {
265        //
266        // Section headers are 8 byte aligned with respect to the beginning of the file stream.
267        //
268        let new_file_offset = (file_offset + 3) & !3;
269        if new_file_offset > file_offset {
270            image_offset += new_file_offset - file_offset;
271            volume_offset += new_file_offset - file_offset;
272            file_offset += new_file_offset - file_offset;
273        }
274
275        let sh = EFI_COMMON_SECTION_HEADER::read_from_prefix(&image[image_offset as usize..])
276            .ok()?
277            .0; // TODO: zerocopy: use-rest-of-range, option-to-error (https://github.com/microsoft/openvmm/issues/759)
278        if sh.typ == EFI_SECTION_PE32 {
279            let pe_offset = pe_get_entry_point_offset(
280                &image[image_offset as usize + size_of::<EFI_COMMON_SECTION_HEADER>()..],
281            )?;
282            image_offset += size_of::<EFI_COMMON_SECTION_HEADER>() as u64 + pe_offset as u64;
283            break;
284        }
285        image_offset += expand_3byte_integer(sh.size);
286        volume_offset += expand_3byte_integer(sh.size);
287        file_offset += expand_3byte_integer(sh.size);
288    }
289
290    Some(image_offset)
291}
292
293/// Definitions shared by UEFI and the loader when loaded with parameters passed in IGVM format.
294mod igvm {
295    use zerocopy::FromBytes;
296
297    use zerocopy::Immutable;
298    use zerocopy::IntoBytes;
299    use zerocopy::KnownLayout;
300
301    /// The structure used to tell UEFI where the IGVM loaded parameters are.
302    #[repr(C)]
303    #[derive(IntoBytes, Immutable, KnownLayout, FromBytes)]
304    pub struct UEFI_IGVM_PARAMETER_INFO {
305        pub parameter_page_count: u32,
306        pub cpuid_pages_offset: u32,
307        pub vp_context_page_number: u64,
308        pub loader_block_offset: u32,
309        pub command_line_offset: u32,
310        pub command_line_page_count: u32,
311        pub memory_map_offset: u32,
312        pub memory_map_page_count: u32,
313        pub madt_offset: u32,
314        pub madt_page_count: u32,
315        pub srat_offset: u32,
316        pub srat_page_count: u32,
317        pub maximum_processor_count: u32,
318        pub uefi_memory_map_offset: u32,
319        pub uefi_memory_map_page_count: u32,
320    }
321
322    pub const UEFI_IGVM_LOADER_BLOCK_NUMBER_OF_PROCESSORS_FIELD_OFFSET: usize = 0;
323}
324
325#[derive(Debug, Error)]
326pub enum Error {
327    #[error("Firmware size invalid")]
328    InvalidImageSize,
329    #[error("Unable to find SEC volume entry point")]
330    NoSecEntryPoint,
331    #[error("Invalid shared gpa boundary")]
332    InvalidSharedGpaBoundary,
333    #[error("Invalid config type")]
334    InvalidConfigType(String),
335    #[error("Importer error")]
336    Importer(#[source] anyhow::Error),
337    #[error("PageTableBuilder: {0}")]
338    PageTableBuilder(#[from] page_table::Error),
339}
340
341#[derive(Debug)]
342pub enum ConfigType {
343    ConfigBlob(config::Blob),
344    Igvm,
345    None,
346}
347
348#[derive(Debug)]
349pub struct LoadInfo {
350    /// The GPA the firmware was loaded at.
351    pub firmware_base: u64,
352    /// The size of the firmware image loaded, in bytes.
353    pub firmware_size: u64,
354    /// The total size used by the loader starting at the firmware_base,
355    /// including the firmware image and misc data, in bytes.
356    pub total_size: u64,
357}
358
359pub mod x86_64 {
360    use super::ConfigType;
361    use super::Error;
362    use super::LoadInfo;
363    use crate::common::DEFAULT_GDT_SIZE;
364    use crate::common::import_default_gdt;
365    use crate::cpuid::HV_PSP_CPUID_PAGE;
366    use crate::importer::BootPageAcceptance;
367    use crate::importer::IgvmParameterType;
368    use crate::importer::ImageLoad;
369    use crate::importer::IsolationType;
370    use crate::importer::StartupMemoryType;
371    use crate::importer::X86Register;
372    use crate::uefi::SEC_FIRMWARE_VOLUME_OFFSET;
373    use crate::uefi::get_sec_entry_point_offset;
374    use hvdef::HV_PAGE_SIZE;
375    use page_table::IdentityMapSize;
376    use page_table::x64::IdentityMapBuilder;
377    use page_table::x64::PAGE_TABLE_MAX_BYTES;
378    use page_table::x64::PAGE_TABLE_MAX_COUNT;
379    use page_table::x64::PageTable;
380    use page_table::x64::align_up_to_page_size;
381    use zerocopy::FromZeros;
382    use zerocopy::IntoBytes;
383
384    pub const IMAGE_SIZE: u64 = 0x00600000; // 6 MB. See MsvmPkg\MsvmPkgX64.fdf
385    const IMAGE_GPA_BASE: u64 = 0x100000; // 1MB
386    const PAGE_TABLE_GPA_BASE: u64 = IMAGE_GPA_BASE + IMAGE_SIZE; // 7MB - 0x700000
387    const PAGE_TABLE_SIZE: u64 = HV_PAGE_SIZE * 6;
388    const GDT_GPA_BASE: u64 = PAGE_TABLE_GPA_BASE + PAGE_TABLE_SIZE; // 0x707000
389    const MISC_PAGES_GPA_BASE: u64 = GDT_GPA_BASE + DEFAULT_GDT_SIZE; // 0x707000
390    const MISC_PAGES_SIZE: u64 = HV_PAGE_SIZE * 2;
391    pub const CONFIG_BLOB_GPA_BASE: u64 = MISC_PAGES_GPA_BASE + MISC_PAGES_SIZE; // 0x709000
392
393    /// Load a UEFI image with the provided config type.
394    pub fn load(
395        importer: &mut dyn ImageLoad<X86Register>,
396        image: &[u8],
397        config: ConfigType,
398    ) -> Result<LoadInfo, Error> {
399        if image.len() != IMAGE_SIZE as usize {
400            return Err(Error::InvalidImageSize);
401        }
402
403        let sec_entry_point = get_sec_entry_point_offset(image).ok_or(Error::NoSecEntryPoint)?;
404
405        let isolation = importer.isolation_config();
406
407        // Build the page tables. This depends on if we have a paravisor present or not:
408        //      - If this is an SNP VM with no paravisor, then build a set of page tables
409        //        to map the bottom 4GB of memory with shared visibility.
410        //      - Otherwise, build the standard UEFI page tables. Bottom 4GB of address space,
411        //        identity mapped with 2 MB pages.
412        let mut page_table_work_buffer: Vec<PageTable> =
413            vec![PageTable::new_zeroed(); PAGE_TABLE_MAX_COUNT];
414        let mut page_tables: Vec<u8> = vec![0; PAGE_TABLE_MAX_BYTES];
415        let page_table_builder = IdentityMapBuilder::new(
416            PAGE_TABLE_GPA_BASE,
417            IdentityMapSize::Size4Gb,
418            page_table_work_buffer.as_mut_slice(),
419            page_tables.as_mut_slice(),
420        )?;
421        let mut shared_vis_page_table_work_buffer: Vec<PageTable> = Vec::new();
422        let mut shared_vis_page_tables: Vec<u8> = Vec::new();
423        let (page_tables, shared_vis_page_tables) =
424            if isolation.isolation_type == IsolationType::Snp && !isolation.paravisor_present {
425                if let ConfigType::ConfigBlob(_) = config {
426                    return Err(Error::InvalidConfigType(
427                        "Enlightened UEFI must use IGVM parameters".into(),
428                    ));
429                }
430
431                let shared_vis_page_table_gpa = CONFIG_BLOB_GPA_BASE + HV_PAGE_SIZE;
432                let shared_gpa_boundary_bits = isolation
433                    .shared_gpa_boundary_bits
434                    .ok_or(Error::InvalidSharedGpaBoundary)?;
435                let shared_gpa_boundary = 1 << shared_gpa_boundary_bits;
436
437                shared_vis_page_table_work_buffer
438                    .resize(PAGE_TABLE_MAX_COUNT, PageTable::new_zeroed());
439                shared_vis_page_tables.resize(PAGE_TABLE_MAX_BYTES, 0);
440                let shared_vis_builder = IdentityMapBuilder::new(
441                    shared_vis_page_table_gpa,
442                    IdentityMapSize::Size4Gb,
443                    shared_vis_page_table_work_buffer.as_mut_slice(),
444                    shared_vis_page_tables.as_mut_slice(),
445                )?
446                .with_address_bias(shared_gpa_boundary);
447
448                // The extra page tables are placed after the first config blob
449                // page.  They will be accounted for when the IGVM parameters are
450                // built.
451                let shared_vis_page_tables = shared_vis_builder.build();
452
453                let page_tables = page_table_builder
454                    .with_pml4e_link((shared_vis_page_table_gpa, shared_gpa_boundary))
455                    .build();
456
457                (page_tables, Some(shared_vis_page_tables))
458            } else {
459                let page_tables = page_table_builder.build();
460                (page_tables, None)
461            };
462
463        // Size must match expected compiled constant
464        assert_eq!(page_tables.len(), PAGE_TABLE_SIZE as usize);
465
466        // Import image, page tables, GDT entries.
467        let image_page_count = image.len() as u64 / HV_PAGE_SIZE;
468        importer
469            .import_pages(
470                IMAGE_GPA_BASE / HV_PAGE_SIZE,
471                image_page_count,
472                "uefi-image",
473                BootPageAcceptance::Exclusive,
474                image,
475            )
476            .map_err(Error::Importer)?;
477
478        let mut total_page_count = IMAGE_GPA_BASE / HV_PAGE_SIZE + image_page_count;
479
480        importer
481            .import_pages(
482                PAGE_TABLE_GPA_BASE / HV_PAGE_SIZE,
483                PAGE_TABLE_SIZE / HV_PAGE_SIZE,
484                "uefi-page-tables",
485                BootPageAcceptance::Exclusive,
486                page_tables,
487            )
488            .map_err(Error::Importer)?;
489
490        total_page_count += PAGE_TABLE_SIZE / HV_PAGE_SIZE;
491
492        // The default GDT is used with a page count of one.
493        assert_eq!(DEFAULT_GDT_SIZE, HV_PAGE_SIZE);
494        import_default_gdt(importer, GDT_GPA_BASE / HV_PAGE_SIZE).map_err(Error::Importer)?;
495        total_page_count += DEFAULT_GDT_SIZE / HV_PAGE_SIZE;
496
497        // Reserve free pages. Currently these are only used by UEFI PEI for making hypercalls.
498        importer
499            .import_pages(
500                MISC_PAGES_GPA_BASE / HV_PAGE_SIZE,
501                MISC_PAGES_SIZE / HV_PAGE_SIZE,
502                "uefi-misc-pages",
503                BootPageAcceptance::Exclusive,
504                &[],
505            )
506            .map_err(Error::Importer)?;
507
508        total_page_count += MISC_PAGES_SIZE / HV_PAGE_SIZE;
509
510        // Import the config blobg, if set. Some callers may not load UEFI
511        // configuration at this time, such as if running with a paravisor.
512        match config {
513            ConfigType::Igvm => {
514                total_page_count += set_igvm_parameters(
515                    importer,
516                    CONFIG_BLOB_GPA_BASE / HV_PAGE_SIZE,
517                    match isolation.isolation_type {
518                        IsolationType::Snp => shared_vis_page_tables
519                            .as_ref()
520                            .expect("should be shared vis page tables"),
521                        _ => &[],
522                    },
523                )?
524            }
525            ConfigType::ConfigBlob(config) => {
526                let data = config.complete();
527                assert!(!data.is_empty());
528                let config_blob_page_count = (data.len() as u64).div_ceil(HV_PAGE_SIZE);
529                importer
530                    .import_pages(
531                        CONFIG_BLOB_GPA_BASE / HV_PAGE_SIZE,
532                        config_blob_page_count,
533                        "uefi-config-blob",
534                        BootPageAcceptance::Exclusive,
535                        &data,
536                    )
537                    .map_err(Error::Importer)?;
538
539                total_page_count += config_blob_page_count;
540            }
541            ConfigType::None => {}
542        }
543
544        // UEFI expects that the memory from GPA 0 up until the end of the config
545        // blob is present, at a minimum. Note that ImageGpaBase is not 0.
546        importer
547            .verify_startup_memory_available(0, total_page_count, StartupMemoryType::Ram)
548            .map_err(Error::Importer)?;
549
550        let mut import_reg = |register| {
551            importer
552                .import_vp_register(register)
553                .map_err(Error::Importer)
554        };
555
556        // Set CR0
557        import_reg(X86Register::Cr0(
558            x86defs::X64_CR0_PG | x86defs::X64_CR0_NE | x86defs::X64_CR0_MP | x86defs::X64_CR0_PE,
559        ))?;
560
561        // Set CR3 to point to page table which starts right after the image.
562        import_reg(X86Register::Cr3(PAGE_TABLE_GPA_BASE))?;
563
564        // Set CR4
565        import_reg(X86Register::Cr4(
566            x86defs::X64_CR4_PAE
567                | x86defs::X64_CR4_MCE
568                | x86defs::X64_CR4_FXSR
569                | x86defs::X64_CR4_XMMEXCPT,
570        ))?;
571
572        // Set EFER to LME, LMA, and NXE for 64 bit mode.
573        import_reg(X86Register::Efer(
574            x86defs::X64_EFER_LMA | x86defs::X64_EFER_LME | x86defs::X64_EFER_NXE,
575        ))?;
576
577        // Set PAT
578        import_reg(X86Register::Pat(x86defs::X86X_MSR_DEFAULT_PAT))?;
579
580        // Set register state to values SEC entry point expects.
581        // RBP - start of BFV (sec FV)
582        import_reg(X86Register::Rbp(
583            IMAGE_GPA_BASE + SEC_FIRMWARE_VOLUME_OFFSET,
584        ))?;
585
586        // Set RIP to SEC entry point.
587        import_reg(X86Register::Rip(IMAGE_GPA_BASE + sec_entry_point))?;
588
589        // Set R8-R11 to the hypervisor isolation CPUID leaf values.
590        let isolation_cpuid = isolation.get_cpuid();
591
592        import_reg(X86Register::R8(isolation_cpuid.eax as u64))?;
593        import_reg(X86Register::R9(isolation_cpuid.ebx as u64))?;
594        import_reg(X86Register::R10(isolation_cpuid.ecx as u64))?;
595        import_reg(X86Register::R11(isolation_cpuid.edx as u64))?;
596
597        // Enable MTRRs, default MTRR is uncached, and set lowest 640KB as WB
598        import_reg(X86Register::MtrrDefType(0xc00))?;
599        import_reg(X86Register::MtrrFix64k00000(0x0606060606060606))?;
600        import_reg(X86Register::MtrrFix16k80000(0x0606060606060606))?;
601
602        Ok(LoadInfo {
603            firmware_base: IMAGE_GPA_BASE,
604            firmware_size: image.len() as u64,
605            total_size: total_page_count * HV_PAGE_SIZE,
606        })
607    }
608
609    /// A simple page allocator that supports allocating pages counting up from a base page.
610    struct PageAllocator {
611        base: u32,
612        total_count: u32,
613    }
614
615    impl PageAllocator {
616        /// Create a `PageAllocator` starting at the given page `base`.
617        fn new(base: u32) -> PageAllocator {
618            PageAllocator {
619                base,
620                total_count: 0,
621            }
622        }
623
624        /// Allocate `count` number of pages. Returns the base page number for the allocation.
625        fn allocate(&mut self, count: u32) -> u32 {
626            let allocation = self.base + self.total_count;
627            self.total_count += count;
628
629            allocation
630        }
631
632        /// Get the total number of pages allocated.
633        fn total(&self) -> u32 {
634            self.total_count
635        }
636    }
637
638    /// Construct the UEFI parameter information in IGVM format. `config_area_base_page` specifies the GPA page number
639    /// at the start of the config region. The number of pages used in the config region is returned.
640    fn set_igvm_parameters(
641        importer: &mut dyn ImageLoad<X86Register>,
642        config_area_base_page: u64,
643        shared_visibility_page_tables: &[u8],
644    ) -> Result<u64, Error> {
645        let mut parameter_info = super::igvm::UEFI_IGVM_PARAMETER_INFO::new_zeroed();
646
647        // IGVM UEFI_IGVM_PARAMETER_INFO page offsets are relative to 1, as the first page is taken by the
648        // UEFI_IGVM_PARAMETER_INFO structure. Allocate a page for the UEFI_IGVM_PARAMETER_INFO structure.
649        let mut allocator = PageAllocator::new(0);
650        allocator.allocate(1);
651
652        // Set up the parameter info structure with offsets to each of the
653        // additional parameters. Each table allocates a constant number of
654        // pages.
655        let table_page_count = 20;
656
657        // The first structure is the loader block, which happens after the parameter info structure and shared
658        // visibility page tables.
659        let page_table_page_count =
660            align_up_to_page_size(shared_visibility_page_tables.len() as u64) / HV_PAGE_SIZE;
661        let page_table_offset = allocator.allocate(page_table_page_count as u32);
662        parameter_info.loader_block_offset = allocator.allocate(1);
663
664        let command_line_page_count = 1;
665        parameter_info.command_line_offset = allocator.allocate(command_line_page_count);
666        parameter_info.command_line_page_count = command_line_page_count;
667
668        parameter_info.memory_map_offset = allocator.allocate(table_page_count);
669        parameter_info.memory_map_page_count = table_page_count;
670
671        parameter_info.madt_offset = allocator.allocate(table_page_count);
672        parameter_info.madt_page_count = table_page_count;
673
674        parameter_info.srat_offset = allocator.allocate(table_page_count);
675        parameter_info.srat_page_count = table_page_count;
676
677        // Reserve additional pre-accepted pages for UEFI to use to reconstruct
678        // portions of the config blob.
679        parameter_info.uefi_memory_map_offset = allocator.allocate(table_page_count);
680        parameter_info.uefi_memory_map_page_count = table_page_count;
681
682        // If this is an SNP image with no paravisor, then reserve additional pages as required.
683        let isolation = importer.isolation_config();
684        if isolation.isolation_type == IsolationType::Snp {
685            // NOTE: Currently UEFI expects this parameter load style to have no paravisor. Disallow that here.
686            if isolation.paravisor_present {
687                return Err(Error::InvalidConfigType(
688                    "IGVM ConfigType specified but paravisor is present.".into(),
689                ));
690            }
691
692            // Supply the address of the parameter info block so it can be used
693            // before PEI parses the config information.
694            importer
695                .import_vp_register(X86Register::R12(config_area_base_page * HV_PAGE_SIZE))
696                .map_err(Error::Importer)?;
697
698            // Reserve two pages to hold CPUID information. The first CPUID page
699            // contains initialized data to query CPUID leaves. The second page
700            // contains no data, as it will be populated by the host when the
701            // image is loaded.
702            parameter_info.cpuid_pages_offset = allocator.allocate(2);
703
704            let cpuid_page = create_snp_cpuid_page();
705
706            importer
707                .import_pages(
708                    config_area_base_page + parameter_info.cpuid_pages_offset as u64,
709                    1,
710                    "uefi-cpuid-page",
711                    BootPageAcceptance::CpuidPage,
712                    cpuid_page.as_bytes(),
713                )
714                .map_err(Error::Importer)?;
715
716            importer
717                .import_pages(
718                    config_area_base_page + parameter_info.cpuid_pages_offset as u64 + 1,
719                    1,
720                    "uefi-cpuid-extended-page",
721                    BootPageAcceptance::CpuidExtendedStatePage,
722                    &[],
723                )
724                .map_err(Error::Importer)?;
725
726            // Reserve a page to use to hold the VMSA.  This must be reported to
727            // UEFI so that the page can be marked as a permanent firmware
728            // allocation.
729            //
730            // Note that this page must not be counted within the size of the
731            // config block, since it has different memory protection properties.
732            // The first page following the config block is chosen for the
733            // allocation.
734            let vp_context_page_number = config_area_base_page + allocator.total() as u64;
735            importer
736                .set_vp_context_page(vp_context_page_number)
737                .map_err(Error::Importer)?;
738
739            parameter_info.vp_context_page_number = vp_context_page_number;
740        } else {
741            // If this is not an SNP image, then the VP context page does not
742            // need to be reported to UEFI. Put in the TDX reset page value for
743            // consistency with old code; this probably is unnecessary (or the
744            // UEFI firmware should just be improved to not need this).
745            parameter_info.vp_context_page_number = 0xfffff;
746        }
747
748        // Encode the total amount of pages used by all parameters.
749        parameter_info.parameter_page_count = allocator.total();
750
751        importer
752            .import_pages(
753                config_area_base_page,
754                1,
755                "uefi-config-base-page",
756                BootPageAcceptance::Exclusive,
757                parameter_info.as_bytes(),
758            )
759            .map_err(Error::Importer)?;
760
761        importer
762            .import_pages(
763                config_area_base_page + parameter_info.uefi_memory_map_offset as u64,
764                parameter_info.uefi_memory_map_page_count as u64,
765                "uefi-memory-map-scratch",
766                BootPageAcceptance::ExclusiveUnmeasured,
767                &[],
768            )
769            .map_err(Error::Importer)?;
770
771        let loader_block = importer
772            .create_parameter_area(
773                config_area_base_page + parameter_info.loader_block_offset as u64,
774                1,
775                "uefi-loader-block",
776            )
777            .map_err(Error::Importer)?;
778        importer
779            .import_parameter(
780                loader_block,
781                super::igvm::UEFI_IGVM_LOADER_BLOCK_NUMBER_OF_PROCESSORS_FIELD_OFFSET as u32,
782                IgvmParameterType::VpCount,
783            )
784            .map_err(Error::Importer)?;
785
786        let command_line = importer
787            .create_parameter_area(
788                config_area_base_page + parameter_info.command_line_offset as u64,
789                parameter_info.command_line_page_count,
790                "uefi-command-line",
791            )
792            .map_err(Error::Importer)?;
793        importer
794            .import_parameter(command_line, 0, IgvmParameterType::CommandLine)
795            .map_err(Error::Importer)?;
796
797        let memory_map = importer
798            .create_parameter_area(
799                config_area_base_page + parameter_info.memory_map_offset as u64,
800                parameter_info.memory_map_page_count,
801                "uefi-memory-map",
802            )
803            .map_err(Error::Importer)?;
804        importer
805            .import_parameter(memory_map, 0, IgvmParameterType::MemoryMap)
806            .map_err(Error::Importer)?;
807
808        let madt = importer
809            .create_parameter_area(
810                config_area_base_page + parameter_info.madt_offset as u64,
811                parameter_info.madt_page_count,
812                "uefi-madt",
813            )
814            .map_err(Error::Importer)?;
815        importer
816            .import_parameter(madt, 0, IgvmParameterType::Madt)
817            .map_err(Error::Importer)?;
818
819        let srat = importer
820            .create_parameter_area(
821                config_area_base_page + parameter_info.srat_offset as u64,
822                parameter_info.srat_page_count,
823                "uefi-srat",
824            )
825            .map_err(Error::Importer)?;
826        importer
827            .import_parameter(srat, 0, IgvmParameterType::Srat)
828            .map_err(Error::Importer)?;
829
830        if page_table_page_count != 0 {
831            importer
832                .import_pages(
833                    config_area_base_page + page_table_offset as u64,
834                    page_table_page_count,
835                    "uefi-igvm-page-tables",
836                    BootPageAcceptance::Exclusive,
837                    shared_visibility_page_tables,
838                )
839                .map_err(Error::Importer)?;
840        }
841
842        Ok(allocator.total() as u64)
843    }
844
845    /// Create a hypervisor SNP CPUID page with the default values.
846    fn create_snp_cpuid_page() -> HV_PSP_CPUID_PAGE {
847        let mut cpuid_page = HV_PSP_CPUID_PAGE::default();
848
849        for (i, required_leaf) in crate::cpuid::SNP_REQUIRED_CPUID_LEAF_LIST_UEFI
850            .iter()
851            .enumerate()
852        {
853            cpuid_page.cpuid_leaf_info[i].eax_in = required_leaf.eax;
854            cpuid_page.cpuid_leaf_info[i].eax_out = required_leaf.ecx;
855            cpuid_page.count += 1;
856        }
857
858        cpuid_page
859    }
860}
861
862pub mod aarch64 {
863    use super::ConfigType;
864    use super::Error;
865    use super::LoadInfo;
866    use crate::importer::Aarch64Register;
867    use crate::importer::BootPageAcceptance;
868    use crate::importer::ImageLoad;
869    use aarch64defs::Cpsr64;
870    use hvdef::HV_PAGE_SIZE;
871
872    use zerocopy::IntoBytes;
873
874    pub const IMAGE_SIZE: u64 = 0x800000;
875    pub const CONFIG_BLOB_GPA_BASE: u64 = 0x824000;
876
877    /// Load a UEFI image with the provided config type.
878    pub fn load(
879        importer: &mut dyn ImageLoad<Aarch64Register>,
880        image: &[u8],
881        config: ConfigType,
882    ) -> Result<LoadInfo, Error> {
883        if image.len() != IMAGE_SIZE as usize {
884            return Err(Error::InvalidImageSize);
885        }
886
887        const BYTES_2MB: u64 = 0x200000;
888
889        let image_size = (image.len() as u64 + BYTES_2MB - 1) & !(BYTES_2MB - 1);
890        importer
891            .import_pages(
892                0,
893                image_size / HV_PAGE_SIZE,
894                "uefi-image",
895                BootPageAcceptance::Exclusive,
896                image,
897            )
898            .map_err(Error::Importer)?;
899
900        // The stack.
901        let stack_offset = image_size;
902        let stack_size = 32 * HV_PAGE_SIZE;
903        let stack_end = stack_offset + stack_size;
904        importer
905            .import_pages(
906                stack_offset / HV_PAGE_SIZE,
907                stack_size / HV_PAGE_SIZE,
908                "uefi-stack",
909                BootPageAcceptance::Exclusive,
910                &[],
911            )
912            .map_err(Error::Importer)?;
913
914        // The page tables.
915        let page_table_offset = stack_end;
916        let page_tables = page_tables(page_table_offset, 1 << 30 /* TODO */);
917        importer
918            .import_pages(
919                page_table_offset / HV_PAGE_SIZE,
920                page_tables.as_bytes().len() as u64 / HV_PAGE_SIZE,
921                "uefi-page-tables",
922                BootPageAcceptance::Exclusive,
923                page_tables.as_bytes(),
924            )
925            .map_err(Error::Importer)?;
926
927        let blob_offset = CONFIG_BLOB_GPA_BASE;
928
929        // The config blob.
930        let blob_size = match config {
931            ConfigType::ConfigBlob(blob) => {
932                let blob = blob.complete();
933                let blob_size = (blob.len() as u64 + HV_PAGE_SIZE - 1) & !(HV_PAGE_SIZE - 1);
934                importer
935                    .import_pages(
936                        blob_offset / HV_PAGE_SIZE,
937                        blob_size / HV_PAGE_SIZE,
938                        "uefi-config-blob",
939                        BootPageAcceptance::Exclusive,
940                        &blob,
941                    )
942                    .map_err(Error::Importer)?;
943
944                blob_size
945            }
946            ConfigType::None => 0,
947            ConfigType::Igvm => {
948                return Err(Error::InvalidConfigType("igvm not supported".to_owned()));
949            }
950        };
951
952        let total_size = blob_offset + blob_size;
953
954        let mut import_reg = |reg| importer.import_vp_register(reg).map_err(Error::Importer);
955
956        import_reg(Aarch64Register::Cpsr(
957            Cpsr64::new().with_sp(true).with_el(1).into(),
958        ))?;
959        import_reg(Aarch64Register::X0(0x1000))?;
960        import_reg(Aarch64Register::Pc(0x1000))?;
961        import_reg(Aarch64Register::X1(stack_end))?;
962
963        import_reg(Aarch64Register::Ttbr0El1(page_table_offset))?;
964
965        // Memory attribute indirection register.
966        const ARM64_MAIR_CACHE_WBWA: u64 = 0xff;
967        const ARM64_MAIR_CACHE_NC: u64 = 0x00;
968        const ARM64_MAIR_CACHE_WTNA: u64 = 0xaa;
969        const ARM64_MAIR_CACHE_WC: u64 = 0x44;
970
971        import_reg(Aarch64Register::MairEl1(
972            ARM64_MAIR_CACHE_WBWA
973                | (ARM64_MAIR_CACHE_NC << 8)
974                | (ARM64_MAIR_CACHE_WTNA << 16)
975                | (ARM64_MAIR_CACHE_WC << 24)
976                | (ARM64_MAIR_CACHE_WBWA << 32)
977                | (ARM64_MAIR_CACHE_NC << 40)
978                | (ARM64_MAIR_CACHE_WTNA << 48)
979                | (ARM64_MAIR_CACHE_WC << 56),
980        ))?;
981
982        // System control register.
983        const ARM64_SCTLR_M: u64 = 0x00000001;
984        const ARM64_SCTLR_C: u64 = 0x00000004;
985        const ARM64_SCTLR_RES1_11: u64 = 0x00000800;
986        const ARM64_SCTLR_I: u64 = 0x00001000;
987        const ARM64_SCTLR_RES1_20: u64 = 0x00100000;
988        const ARM64_SCTLR_RES1_22: u64 = 0x00400000;
989        const ARM64_SCTLR_RES1_23: u64 = 0x00800000;
990        const ARM64_SCTLR_RES1_28: u64 = 0x10000000;
991        const ARM64_SCTLR_RES1_29: u64 = 0x20000000;
992
993        import_reg(Aarch64Register::SctlrEl1(
994            ARM64_SCTLR_M
995                | ARM64_SCTLR_C
996                | ARM64_SCTLR_I
997                | ARM64_SCTLR_RES1_11
998                | ARM64_SCTLR_RES1_20
999                | ARM64_SCTLR_RES1_22
1000                | ARM64_SCTLR_RES1_23
1001                | ARM64_SCTLR_RES1_28
1002                | ARM64_SCTLR_RES1_29,
1003        ))?;
1004
1005        // Translation control register.
1006
1007        const ARM64_TCR_IRGN0_WBWA: u64 = 0x0000000000000100;
1008        const ARM64_TCR_ORGN0_WBWA: u64 = 0x0000000000000400;
1009        const ARM64_TCR_SH0_INNER_SHARED: u64 = 0x0000000000003000;
1010        const ARM64_TCR_TG0_4K: u64 = 0x0000000000000000;
1011        const ARM64_TCR_EPD1: u64 = 0x0000000000800000;
1012        const ARM64_TCR_T0SZ_SHIFT: u32 = 0;
1013        const ARM64_TCR_T1SZ_SHIFT: u32 = 16;
1014
1015        import_reg(Aarch64Register::TcrEl1(
1016            ARM64_TCR_EPD1
1017                | ARM64_TCR_TG0_4K
1018                | ARM64_TCR_SH0_INNER_SHARED
1019                | ARM64_TCR_ORGN0_WBWA
1020                | ARM64_TCR_IRGN0_WBWA
1021                | (16 << ARM64_TCR_T0SZ_SHIFT)
1022                | (16 << ARM64_TCR_T1SZ_SHIFT),
1023        ))?;
1024
1025        Ok(LoadInfo {
1026            firmware_base: 0,
1027            firmware_size: image.len() as u64,
1028            total_size,
1029        })
1030    }
1031
1032    const PTE_VALID: u64 = 1 << 0;
1033    const PTE_NOT_LARGE: u64 = 1 << 1;
1034    const PTE_MAIR_WB: u64 = 0 << 2;
1035    const PTE_MAIR_UC: u64 = 1 << 2;
1036    const PTE_SHARABILITY_INNER: u64 = 3 << 8;
1037    const PTE_ACCESSED: u64 = 1 << 10;
1038    const PTE_USER_NX: u64 = 1 << 54;
1039
1040    fn large_leaf_entry(normal: bool, address: u64) -> u64 {
1041        address
1042            | PTE_VALID
1043            | PTE_ACCESSED
1044            | PTE_SHARABILITY_INNER
1045            | PTE_USER_NX
1046            | if normal { PTE_MAIR_WB } else { PTE_MAIR_UC }
1047    }
1048
1049    fn non_leaf_entry(address: u64) -> u64 {
1050        address | PTE_VALID | PTE_NOT_LARGE
1051    }
1052
1053    fn leaf_entry(normal: bool, address: u64) -> u64 {
1054        address
1055            | PTE_VALID
1056            | PTE_ACCESSED
1057            | PTE_NOT_LARGE
1058            | PTE_SHARABILITY_INNER
1059            | PTE_USER_NX
1060            | if normal { PTE_MAIR_WB } else { PTE_MAIR_UC }
1061    }
1062
1063    fn table_index(va: u64, level: u32) -> usize {
1064        let index = va >> (9 * (3 - level) + 12);
1065        let index = index & ((1 << 9) - 1);
1066        index as usize
1067    }
1068
1069    fn page_tables(address: u64, end_of_ram: u64) -> Vec<[u64; 512]> {
1070        const PT_SIZE: u64 = 4096;
1071        const VA_4GB: u64 = 1 << 32;
1072        const VA_1GB: u64 = 1 << 30;
1073        const VA_2MB: u64 = 2 << 20;
1074        const VA_4KB: u64 = 4 << 10;
1075
1076        let mut buffer = vec![[0u64; PT_SIZE as usize / 8]; 4];
1077        let [level0, level1, level2, level3] = buffer.as_mut_slice() else {
1078            unreachable!()
1079        };
1080
1081        // Allocate temporary buffer to hold page tables. We need 4 page tables:
1082        // - PML4 table (level 0 table in ARM terminology).
1083        // - PDP table (level 1 table).
1084        // - PD table (level 2 table) to map the 1 GB region that contains the
1085        //   split between normal and device memory.
1086        // - PT table (level 3 table) to map the 2 MB region that contains the
1087        //   split between normal and device memory.
1088
1089        // Link level 1 translation table.
1090        level0[0] = non_leaf_entry(address + PT_SIZE);
1091
1092        // Create an identity map for the address space from 0 to 4 GB.
1093        // The range [0, 4GB - MMIO Space Size) is mapped as normal memory, the
1094        // range [4 GB - MMIO Space Size, 4 GB) is mapped as device memory.
1095
1096        let mut normal = true;
1097        let mut va = 0;
1098        let mut end_va = end_of_ram;
1099        while va < VA_4GB {
1100            //
1101            // Switch to device memory if we are are within the MMIO space.
1102            //
1103            if normal && va == end_va {
1104                normal = false;
1105                end_va = VA_4GB;
1106                continue;
1107            }
1108
1109            // Try to use a 1 GB page (level 1 block entry) if possible.
1110            let level1_index = table_index(va, 1);
1111            if level1[level1_index] & PTE_VALID == 0
1112                && ((va & (VA_1GB - 1)) == 0)
1113                && (end_va - va >= VA_1GB)
1114            {
1115                level1[level1_index] = large_leaf_entry(normal, va);
1116                va += VA_1GB;
1117                continue;
1118            }
1119
1120            //
1121            // Allocate and link level 2 translation table (PD) if it does not yet
1122            // exist.
1123            //
1124            if level1[level1_index] & PTE_VALID == 0 {
1125                level1[level1_index] = non_leaf_entry(address + PT_SIZE * 2);
1126            }
1127
1128            //
1129            // Try to use a 2 MB page (level 2 block entry) if possible.
1130            //
1131            let level2_index = table_index(va, 2);
1132            if level2[level2_index] & PTE_VALID == 0
1133                && ((va & (VA_2MB - 1)) == 0)
1134                && (end_va - va >= VA_2MB)
1135            {
1136                level2[level2_index] = large_leaf_entry(normal, va);
1137                va += VA_2MB;
1138                continue;
1139            }
1140
1141            //
1142            // Allocate and link level 1 translation table (PT) if it does not yet
1143            // exist.
1144            //
1145            if level2[level2_index] & PTE_VALID == 0 {
1146                level2[level2_index] = non_leaf_entry(address + PT_SIZE * 3);
1147            }
1148
1149            let level3_index = table_index(va, 3);
1150            level3[level3_index] = leaf_entry(normal, va);
1151            va += VA_4KB;
1152        }
1153
1154        buffer
1155    }
1156}
loader/uefi/mod.rs

loader/uefi/
mod.rs
