flowey_lib_hvlite/
build_ohcldiag_dev.rs1use crate::run_cargo_build::common::CommonProfile;
7use crate::run_cargo_build::common::CommonTriple;
8use flowey::node::prelude::*;
9
10#[derive(Serialize, Deserialize)]
11#[serde(untagged)]
12pub enum OhcldiagDevOutput {
13 LinuxBin {
14 #[serde(rename = "ohcldiag-dev")]
15 bin: PathBuf,
16 #[serde(rename = "ohcldiag-dev.dbg")]
17 dbg: PathBuf,
18 },
19 WindowsBin {
20 #[serde(rename = "ohcldiag-dev.exe")]
21 exe: PathBuf,
22 #[serde(rename = "ohcldiag-dev.pdb")]
23 pdb: PathBuf,
24 },
25}
26
27impl Artifact for OhcldiagDevOutput {}
28
29flowey_request! {
30 pub struct Request {
31 pub target: CommonTriple,
32 pub profile: CommonProfile,
33 pub ohcldiag_dev: WriteVar<OhcldiagDevOutput>,
34 }
35}
36
37new_simple_flow_node!(struct Node);
38
39impl SimpleFlowNode for Node {
40 type Request = Request;
41
42 fn imports(ctx: &mut ImportCtx<'_>) {
43 ctx.import::<crate::run_cargo_build::Node>();
44 ctx.import::<flowey_lib_common::install_dist_pkg::Node>();
45 }
46
47 fn process_request(request: Self::Request, ctx: &mut NodeCtx<'_>) -> anyhow::Result<()> {
48 let Request {
49 target,
50 profile,
51 ohcldiag_dev,
52 } = request;
53 let output = ctx.reqv(|v| crate::run_cargo_build::Request {
54 crate_name: "ohcldiag-dev".into(),
55 out_name: "ohcldiag-dev".into(),
56 crate_type: flowey_lib_common::run_cargo_build::CargoCrateType::Bin,
57 profile: profile.into(),
58 features: [].into(),
59 target: target.as_triple(),
60 no_split_dbg_info: false,
61 extra_env: None,
62 pre_build_deps: Vec::new(),
63 output: v,
64 });
65
66 ctx.emit_minor_rust_step("report built ohcldiag_dev", |ctx| {
67 let ohcldiag_dev = ohcldiag_dev.claim(ctx);
68 let output = output.claim(ctx);
69 move |rt| {
70 let output = match rt.read(output) {
71 crate::run_cargo_build::CargoBuildOutput::WindowsBin { exe, pdb } => {
72 OhcldiagDevOutput::WindowsBin { exe, pdb }
73 }
74 crate::run_cargo_build::CargoBuildOutput::ElfBin { bin, dbg } => {
75 OhcldiagDevOutput::LinuxBin {
76 bin,
77 dbg: dbg.unwrap(),
78 }
79 }
80 _ => unreachable!(),
81 };
82
83 rt.write(ohcldiag_dev, &output);
84 }
85 });
86
87 Ok(())
88 }
89}