acpi/
ssdt.rs

1// Copyright (c) Microsoft Corporation.
2// Licensed under the MIT License.
3
4pub use crate::aml::*;
5use memory_range::MemoryRange;
6use zerocopy::FromBytes;
7use zerocopy::Immutable;
8use zerocopy::IntoBytes;
9use zerocopy::KnownLayout;
10
11#[repr(C, packed)]
12#[derive(Copy, Clone, Debug, IntoBytes, Immutable, KnownLayout, FromBytes)]
13pub struct DescriptionHeader {
14    pub signature: u32,
15    _length: u32, // placeholder, filled in during serialization to bytes
16    pub revision: u8,
17    _checksum: u8, // placeholder, filled in during serialization to bytes
18    pub oem_id: [u8; 6],
19    pub oem_table_id: u64,
20    pub oem_revision: u32,
21    pub creator_id: u32,
22    pub creator_rev: u32,
23}
24
25fn encode_pcie_name(mut pcie_index: u32) -> Vec<u8> {
26    assert!(pcie_index < 1000);
27    let mut temp = "PCI0".as_bytes().to_vec();
28    let mut i = temp.len() - 1;
29    while pcie_index > 0 {
30        temp[i] = b'0' + (pcie_index % 10) as u8;
31        pcie_index /= 10;
32        i -= 1;
33    }
34    temp
35}
36
37pub struct Ssdt {
38    description_header: DescriptionHeader,
39    objects: Vec<u8>,
40    pcie_ecam_ranges: Vec<MemoryRange>,
41}
42
43impl Ssdt {
44    pub fn new() -> Self {
45        Self {
46            description_header: DescriptionHeader {
47                signature: u32::from_le_bytes(*b"SSDT"),
48                _length: 0,
49                revision: 2,
50                _checksum: 0,
51                oem_id: *b"MSFTVM",
52                oem_table_id: 0x313054445353, // b'SSDT01'
53                oem_revision: 1,
54                creator_id: u32::from_le_bytes(*b"MSFT"),
55                creator_rev: 0x01000000,
56            },
57            objects: vec![],
58            pcie_ecam_ranges: vec![],
59        }
60    }
61
62    pub fn to_bytes(&self) -> Vec<u8> {
63        let mut byte_stream = Vec::new();
64        byte_stream.extend_from_slice(self.description_header.as_bytes());
65        byte_stream.extend_from_slice(&self.objects);
66
67        // N.B. Certain guest OSes will only probe ECAM ranges if they are
68        // reserved in the resources of an ACPI motherboard device.
69        if !self.pcie_ecam_ranges.is_empty() {
70            let mut vmod = Device::new(b"VMOD");
71            vmod.add_object(&NamedObject::new(b"_HID", &EisaId(*b"PNP0C02")));
72
73            let mut crs = CurrentResourceSettings::new();
74            for ecam_range in &self.pcie_ecam_ranges {
75                crs.add_resource(&QwordMemory::new(
76                    ecam_range.start(),
77                    ecam_range.end() - ecam_range.start(),
78                ));
79            }
80            vmod.add_object(&crs);
81            vmod.append_to_vec(&mut byte_stream);
82        }
83
84        let length = byte_stream.len();
85        byte_stream[4..8].copy_from_slice(&u32::try_from(length).unwrap().to_le_bytes());
86        let mut checksum: u8 = 0;
87        for byte in &byte_stream {
88            checksum = checksum.wrapping_add(*byte);
89        }
90
91        byte_stream[9] = (!checksum).wrapping_add(1);
92        byte_stream
93    }
94
95    pub fn add_object(&mut self, obj: &impl AmlObject) {
96        obj.append_to_vec(&mut self.objects);
97    }
98
99    /// Adds a PCI Express root complex with the specified bus number and MMIO ranges.
100    ///
101    /// ```text
102    /// Device(\_SB.PCI<N>)
103    /// {
104    ///     Name(_HID, PNP0A08)
105    ///     Name(_CID, PNP0A03)
106    ///     Name(_UID, <index>)
107    ///     Name(_SEG, <segment>)
108    ///     Name(_BBN, <bus number>)
109    ///     Name(_CRS, ResourceTemplate()
110    ///     {
111    ///         WordBusNumber(...) // Bus number range
112    ///         QWordMemory() // Low MMIO
113    ///         QWordMemory() // High MMIO
114    ///     })
115    /// }
116    /// ```
117    pub fn add_pcie(
118        &mut self,
119        index: u32,
120        segment: u16,
121        start_bus: u8,
122        end_bus: u8,
123        ecam_range: MemoryRange,
124        low_mmio: MemoryRange,
125        high_mmio: MemoryRange,
126    ) {
127        let mut pcie = Device::new(encode_pcie_name(index).as_slice());
128        pcie.add_object(&NamedObject::new(b"_HID", &EisaId(*b"PNP0A08")));
129        pcie.add_object(&NamedObject::new(b"_CID", &EisaId(*b"PNP0A03")));
130        pcie.add_object(&NamedInteger::new(b"_UID", index.into()));
131        pcie.add_object(&NamedInteger::new(b"_SEG", segment.into()));
132        pcie.add_object(&NamedInteger::new(b"_BBN", start_bus.into()));
133
134        // TODO: Add an _OSC method to grant native PCIe control. Linux ignores
135        // OSC and assumes control, but Windows will skip initialization of
136        // some PCIe features when OSC is not granted.
137
138        let mut crs = CurrentResourceSettings::new();
139        crs.add_resource(&BusNumber::new(
140            start_bus.into(),
141            (end_bus as u16) - (start_bus as u16) + 1,
142        ));
143        crs.add_resource(&QwordMemory::new(
144            low_mmio.start(),
145            low_mmio.end() - low_mmio.start(),
146        ));
147        crs.add_resource(&QwordMemory::new(
148            high_mmio.start(),
149            high_mmio.end() - high_mmio.start(),
150        ));
151        pcie.add_object(&crs);
152
153        self.add_object(&pcie);
154        self.pcie_ecam_ranges.push(ecam_range);
155    }
156}
157
158#[cfg(test)]
159mod tests {
160    use super::*;
161    use crate::aml::test_helpers::verify_expected_bytes;
162
163    pub fn verify_header(bytes: &[u8]) {
164        assert!(bytes.len() >= 36);
165
166        // signature
167        assert_eq!(bytes[0], b'S');
168        assert_eq!(bytes[1], b'S');
169        assert_eq!(bytes[2], b'D');
170        assert_eq!(bytes[3], b'T');
171
172        // length
173        let ssdt_len = u32::from_le_bytes(bytes[4..8].try_into().unwrap());
174        assert_eq!(ssdt_len as usize, bytes.len());
175
176        // revision
177        assert_eq!(bytes[8], 2);
178
179        // Validate checksum bytes[9] by verifying content adds to zero.
180        let mut checksum: u8 = 0;
181        for byte in bytes.iter() {
182            checksum = checksum.wrapping_add(*byte);
183        }
184        assert_eq!(checksum, 0);
185
186        // oem_id
187        assert_eq!(bytes[10], b'M');
188        assert_eq!(bytes[11], b'S');
189        assert_eq!(bytes[12], b'F');
190        assert_eq!(bytes[13], b'T');
191        assert_eq!(bytes[14], b'V');
192        assert_eq!(bytes[15], b'M');
193
194        // oem_table_id
195        assert_eq!(bytes[16], b'S');
196        assert_eq!(bytes[17], b'S');
197        assert_eq!(bytes[18], b'D');
198        assert_eq!(bytes[19], b'T');
199        assert_eq!(bytes[20], b'0');
200        assert_eq!(bytes[21], b'1');
201        assert_eq!(bytes[22], 0);
202        assert_eq!(bytes[23], 0);
203
204        // oem_revision
205        let oem_revision = u32::from_le_bytes(bytes[24..28].try_into().unwrap());
206        assert_eq!(oem_revision, 1);
207
208        // creator_id
209        assert_eq!(bytes[28], b'M');
210        assert_eq!(bytes[29], b'S');
211        assert_eq!(bytes[30], b'F');
212        assert_eq!(bytes[31], b'T');
213
214        // creator_rev
215        let creator_rev = u32::from_le_bytes(bytes[32..36].try_into().unwrap());
216        assert_eq!(creator_rev, 0x01000000);
217    }
218
219    #[test]
220    pub fn verify_pcie_name_encoding() {
221        assert_eq!(encode_pcie_name(0), b"PCI0".to_vec());
222        assert_eq!(encode_pcie_name(1), b"PCI1".to_vec());
223        assert_eq!(encode_pcie_name(2), b"PCI2".to_vec());
224        assert_eq!(encode_pcie_name(54), b"PC54".to_vec());
225        assert_eq!(encode_pcie_name(294), b"P294".to_vec());
226    }
227
228    #[test]
229    fn verify_simple_table() {
230        let mut ssdt = Ssdt::new();
231        let nobj = NamedObject::new(b"_S0", &Package(vec![0, 0]));
232        ssdt.add_object(&nobj);
233        let bytes = ssdt.to_bytes();
234        verify_header(&bytes);
235        verify_expected_bytes(&bytes[36..], &[8, b'_', b'S', b'0', b'_', 0x12, 4, 2, 0, 0]);
236    }
237}
acpi/ssdt.rs

acpi/
ssdt.rs
