acpi/
ssdt.rs

1// Copyright (c) Microsoft Corporation.
2// Licensed under the MIT License.
3
4pub use crate::aml::*;
5use memory_range::MemoryRange;
6use zerocopy::FromBytes;
7use zerocopy::Immutable;
8use zerocopy::IntoBytes;
9use zerocopy::KnownLayout;
10
11#[repr(C, packed)]
12#[derive(Copy, Clone, Debug, IntoBytes, Immutable, KnownLayout, FromBytes)]
13pub struct DescriptionHeader {
14    pub signature: u32,
15    _length: u32, // placeholder, filled in during serialization to bytes
16    pub revision: u8,
17    _checksum: u8, // placeholder, filled in during serialization to bytes
18    pub oem_id: [u8; 6],
19    pub oem_table_id: u64,
20    pub oem_revision: u32,
21    pub creator_id: u32,
22    pub creator_rev: u32,
23}
24
25fn encode_pcie_name(mut pcie_index: u32) -> Vec<u8> {
26    assert!(pcie_index < 1000);
27    let mut temp = "PCI0".as_bytes().to_vec();
28    let mut i = temp.len() - 1;
29    while pcie_index > 0 {
30        temp[i] = b'0' + (pcie_index % 10) as u8;
31        pcie_index /= 10;
32        i -= 1;
33    }
34    temp
35}
36
37pub struct Ssdt {
38    description_header: DescriptionHeader,
39    objects: Vec<u8>,
40    pcie_ecam_ranges: Vec<MemoryRange>,
41}
42
43impl Ssdt {
44    pub fn new() -> Self {
45        Self {
46            description_header: DescriptionHeader {
47                signature: u32::from_le_bytes(*b"SSDT"),
48                _length: 0,
49                revision: 2,
50                _checksum: 0,
51                oem_id: *b"MSFTVM",
52                oem_table_id: 0x313054445353, // b'SSDT01'
53                oem_revision: 1,
54                creator_id: u32::from_le_bytes(*b"MSFT"),
55                creator_rev: 0x01000000,
56            },
57            objects: vec![],
58            pcie_ecam_ranges: vec![],
59        }
60    }
61
62    pub fn to_bytes(&self) -> Vec<u8> {
63        let mut byte_stream = Vec::new();
64        byte_stream.extend_from_slice(self.description_header.as_bytes());
65        byte_stream.extend_from_slice(&self.objects);
66
67        // N.B. Certain guest OSes will only probe ECAM ranges if they are
68        // reserved in the resources of an ACPI motherboard device.
69        if !self.pcie_ecam_ranges.is_empty() {
70            let mut vmod = Device::new(b"VMOD");
71            vmod.add_object(&NamedObject::new(b"_HID", &EisaId(*b"PNP0C02")));
72
73            let mut crs = CurrentResourceSettings::new();
74            for ecam_range in &self.pcie_ecam_ranges {
75                crs.add_resource(&QwordMemory::new(
76                    ecam_range.start(),
77                    ecam_range.end() - ecam_range.start(),
78                ));
79            }
80            vmod.add_object(&crs);
81            vmod.append_to_vec(&mut byte_stream);
82        }
83
84        let length = byte_stream.len();
85        byte_stream[4..8].copy_from_slice(&u32::try_from(length).unwrap().to_le_bytes());
86        let mut checksum: u8 = 0;
87        for byte in &byte_stream {
88            checksum = checksum.wrapping_add(*byte);
89        }
90
91        byte_stream[9] = (!checksum).wrapping_add(1);
92        byte_stream
93    }
94
95    pub fn add_object(&mut self, obj: &impl AmlObject) {
96        obj.append_to_vec(&mut self.objects);
97    }
98
99    /// Adds a PCI Express root complex with the specified bus number and MMIO ranges.
100    ///
101    /// ```text
102    /// Device(\_SB.PCI<N>)
103    /// {
104    ///     Name(_HID, PNP0A08)
105    ///     Name(_UID, <index>)
106    ///     Name(_SEG, <segment>)
107    ///     Name(_BBN, <bus number>)
108    ///     Name(_CRS, ResourceTemplate()
109    ///     {
110    ///         WordBusNumber(...) // Bus number range
111    ///         QWordMemory() // Low MMIO
112    ///         QWordMemory() // High MMIO
113    ///     })
114    /// }
115    /// ```
116    pub fn add_pcie(
117        &mut self,
118        index: u32,
119        segment: u16,
120        start_bus: u8,
121        end_bus: u8,
122        ecam_range: MemoryRange,
123        low_mmio: MemoryRange,
124        high_mmio: MemoryRange,
125    ) {
126        let mut pcie = Device::new(encode_pcie_name(index).as_slice());
127        pcie.add_object(&NamedObject::new(b"_HID", &EisaId(*b"PNP0A08")));
128        pcie.add_object(&NamedInteger::new(b"_UID", index.into()));
129        pcie.add_object(&NamedInteger::new(b"_SEG", segment.into()));
130        pcie.add_object(&NamedInteger::new(b"_BBN", start_bus.into()));
131
132        // TODO: Add an _OSC method to grant native PCIe control. Linux ignores
133        // OSC and assumes control, but Windows will skip initialization of
134        // some PCIe features when OSC is not granted.
135
136        let mut crs = CurrentResourceSettings::new();
137        crs.add_resource(&BusNumber::new(
138            start_bus.into(),
139            (end_bus as u16) - (start_bus as u16) + 1,
140        ));
141        crs.add_resource(&QwordMemory::new(
142            low_mmio.start(),
143            low_mmio.end() - low_mmio.start(),
144        ));
145        crs.add_resource(&QwordMemory::new(
146            high_mmio.start(),
147            high_mmio.end() - high_mmio.start(),
148        ));
149        pcie.add_object(&crs);
150
151        self.add_object(&pcie);
152        self.pcie_ecam_ranges.push(ecam_range);
153    }
154}
155
156#[cfg(test)]
157mod tests {
158    use super::*;
159    use crate::aml::test_helpers::verify_expected_bytes;
160
161    pub fn verify_header(bytes: &[u8]) {
162        assert!(bytes.len() >= 36);
163
164        // signature
165        assert_eq!(bytes[0], b'S');
166        assert_eq!(bytes[1], b'S');
167        assert_eq!(bytes[2], b'D');
168        assert_eq!(bytes[3], b'T');
169
170        // length
171        let ssdt_len = u32::from_le_bytes(bytes[4..8].try_into().unwrap());
172        assert_eq!(ssdt_len as usize, bytes.len());
173
174        // revision
175        assert_eq!(bytes[8], 2);
176
177        // Validate checksum bytes[9] by verifying content adds to zero.
178        let mut checksum: u8 = 0;
179        for byte in bytes.iter() {
180            checksum = checksum.wrapping_add(*byte);
181        }
182        assert_eq!(checksum, 0);
183
184        // oem_id
185        assert_eq!(bytes[10], b'M');
186        assert_eq!(bytes[11], b'S');
187        assert_eq!(bytes[12], b'F');
188        assert_eq!(bytes[13], b'T');
189        assert_eq!(bytes[14], b'V');
190        assert_eq!(bytes[15], b'M');
191
192        // oem_table_id
193        assert_eq!(bytes[16], b'S');
194        assert_eq!(bytes[17], b'S');
195        assert_eq!(bytes[18], b'D');
196        assert_eq!(bytes[19], b'T');
197        assert_eq!(bytes[20], b'0');
198        assert_eq!(bytes[21], b'1');
199        assert_eq!(bytes[22], 0);
200        assert_eq!(bytes[23], 0);
201
202        // oem_revision
203        let oem_revision = u32::from_le_bytes(bytes[24..28].try_into().unwrap());
204        assert_eq!(oem_revision, 1);
205
206        // creator_id
207        assert_eq!(bytes[28], b'M');
208        assert_eq!(bytes[29], b'S');
209        assert_eq!(bytes[30], b'F');
210        assert_eq!(bytes[31], b'T');
211
212        // creator_rev
213        let creator_rev = u32::from_le_bytes(bytes[32..36].try_into().unwrap());
214        assert_eq!(creator_rev, 0x01000000);
215    }
216
217    #[test]
218    pub fn verify_pcie_name_encoding() {
219        assert_eq!(encode_pcie_name(0), b"PCI0".to_vec());
220        assert_eq!(encode_pcie_name(1), b"PCI1".to_vec());
221        assert_eq!(encode_pcie_name(2), b"PCI2".to_vec());
222        assert_eq!(encode_pcie_name(54), b"PC54".to_vec());
223        assert_eq!(encode_pcie_name(294), b"P294".to_vec());
224    }
225
226    #[test]
227    fn verify_simple_table() {
228        let mut ssdt = Ssdt::new();
229        let nobj = NamedObject::new(b"_S0", &Package(vec![0, 0]));
230        ssdt.add_object(&nobj);
231        let bytes = ssdt.to_bytes();
232        verify_header(&bytes);
233        verify_expected_bytes(&bytes[36..], &[8, b'_', b'S', b'0', b'_', 0x12, 4, 2, 0, 0]);
234    }
235}
acpi/ssdt.rs

acpi/
ssdt.rs
