aarch64defs/
gic.rs

1// Copyright (c) Microsoft Corporation.
2// Licensed under the MIT License.
3
4//! Definitions for the Generic Interrupt Controller (GIC) registers.
5
6use bitfield_struct::bitfield;
7use core::ops::Range;
8use open_enum::open_enum;
9
10open_enum! {
11    pub enum GicdRegister: u16 {
12        CTLR = 0x0000,
13        TYPER = 0x0004,
14        IIDR = 0x0008,
15        TYPER2 = 0x000c,
16        STATUSR = 0x0010,
17        SETSPI_NSR = 0x0040,
18        CLRSPI_NSR = 0x0048,
19        SETSPI_SR = 0x0050,
20        CLRSPI_SR = 0x0058,
21        IGROUPR0 = 0x0080,       // 0x80
22        ISENABLER0 = 0x0100,     // 0x80
23        ICENABLER0 = 0x0180,     // 0x80
24        ISPENDR0 = 0x0200,       // 0x80
25        ICPENDR0 = 0x0280,       // 0x80
26        ISACTIVER0 = 0x0300,     // 0x80
27        ICACTIVER0 = 0x0380,     // 0x80
28        IPRIORITYR0 = 0x0400,    // 0x400
29        ITARGETSR0 = 0x0800,     // 0x400
30        ICFGR0 = 0x0c00,         // 0x100
31        IGRPMODR0 = 0x0d00,      // 0x100
32        NSACR0 = 0x0e00,         // 0x100
33        SGIR = 0x0f00,
34        CPENDSGIR0 = 0x0f10,     // 0x10
35        SPENDSGIR0 = 0x0f20,     // 0x10
36        INMIR0 = 0x0f80,         // 0x80
37        IROUTER0 = 0x6000,       // 0x2000, skip first 0x100,
38        PIDR2 = 0xffe8,
39    }
40}
41
42impl GicdRegister {
43    pub const IGROUPR: Range<u16> = Self::IGROUPR0.0..Self::IGROUPR0.0 + 0x80;
44    pub const ISENABLER: Range<u16> = Self::ISENABLER0.0..Self::ISENABLER0.0 + 0x80;
45    pub const ICENABLER: Range<u16> = Self::ICENABLER0.0..Self::ICENABLER0.0 + 0x80;
46    pub const ISPENDR: Range<u16> = Self::ISPENDR0.0..Self::ISPENDR0.0 + 0x80;
47    pub const ICPENDR: Range<u16> = Self::ICPENDR0.0..Self::ICPENDR0.0 + 0x80;
48    pub const ISACTIVER: Range<u16> = Self::ISACTIVER0.0..Self::ISACTIVER0.0 + 0x80;
49    pub const ICACTIVER: Range<u16> = Self::ICACTIVER0.0..Self::ICACTIVER0.0 + 0x80;
50    pub const ICFGR: Range<u16> = Self::ICFGR0.0..Self::ICFGR0.0 + 0x100;
51    pub const IPRIORITYR: Range<u16> = Self::IPRIORITYR0.0..Self::IPRIORITYR0.0 + 0x400;
52    pub const IROUTER: Range<u16> = Self::IROUTER0.0..Self::IROUTER0.0 + 0x2000;
53}
54
55#[bitfield(u32)]
56pub struct GicdTyper {
57    #[bits(5)]
58    pub it_lines_number: u8,
59    #[bits(3)]
60    pub cpu_number: u8,
61    pub espi: bool,
62    pub nmi: bool,
63    pub security_extn: bool,
64    #[bits(5)]
65    pub num_lpis: u8,
66    pub mbis: bool,
67    pub lpis: bool,
68    pub dvis: bool,
69    #[bits(5)]
70    pub id_bits: u8,
71    pub a3v: bool,
72    pub no1n: bool,
73    pub rss: bool,
74    #[bits(5)]
75    pub espi_range: u8,
76}
77
78#[bitfield(u32)]
79pub struct GicdTyper2 {
80    #[bits(5)]
81    pub vid: u8,
82    #[bits(2)]
83    _res5_6: u8,
84    pub vil: bool,
85    pub n_assgi_cap: bool,
86    #[bits(23)]
87    _res9_31: u32,
88}
89
90#[bitfield(u32)]
91pub struct GicdCtlr {
92    pub enable_grp0: bool,
93    pub enable_grp1: bool,
94    #[bits(2)]
95    _res_2_3: u8,
96    pub are: bool,
97    _res_5: bool,
98    pub ds: bool,
99    pub e1nwf: bool,
100    pub n_assgi_req: bool,
101    #[bits(22)]
102    _res_9_30: u32,
103    pub rwp: bool,
104}
105
106open_enum! {
107    pub enum GicrRdRegister: u16 {
108        CTLR = 0x0000,
109        IIDR = 0x0004,
110        TYPER = 0x0008,     // 64 bit
111        STATUSR = 0x0010,
112        WAKER = 0x0014,
113        MPAMIDR = 0x0018,
114        PARTIDR = 0x001c,
115        SETLPIR = 0x0040,   // 64 bit
116        CLRLPIR = 0x0048,   // 64 bit
117        PROPBASER = 0x0070, // 64 bit
118        PENDBASER = 0x0078, // 64 bit
119        INVLPIR = 0x00A0,   // 64 bit
120        SYNCR = 0x00C0,     // 64 bit
121        PIDR2 = 0xffe8,
122    }
123}
124
125open_enum! {
126    pub enum GicrSgiRegister: u16 {
127        IGROUPR0 = 0x0080,
128        ISENABLER0 = 0x0100,
129        ICENABLER0 = 0x0180,
130        ISPENDR0 = 0x0200,
131        ICPENDR0 = 0x0280,
132        ISACTIVER0 = 0x0300,
133        ICACTIVER0 = 0x0380,
134        IPRIORITYR0 = 0x0400, // 0x20
135        ICFGR0 = 0x0c00,
136        ICFGR1 = 0x0c04,
137        IGRPMODR0 = 0x0d00,
138    }
139}
140
141impl GicrSgiRegister {
142    pub const IPRIORITYR: Range<u16> = Self::IPRIORITYR0.0..Self::IPRIORITYR0.0 + 0x20;
143}
144
145#[bitfield(u64)]
146pub struct GicrTyper {
147    pub plpis: bool,
148    pub vlpis: bool,
149    pub dirty: bool,
150    pub direct_lpi: bool,
151    pub last: bool,
152    pub dpgs: bool,
153    pub mpam: bool,
154    pub rvpeid: bool,
155    pub processor_number: u16,
156    #[bits(2)]
157    pub common_lpi_aff: u8,
158    pub vsgi: bool,
159    #[bits(5)]
160    pub ppi_num: u8,
161    pub aff0: u8,
162    pub aff1: u8,
163    pub aff2: u8,
164    pub aff3: u8,
165}
166
167#[bitfield(u32)]
168pub struct GicrCtlr {
169    pub enable_lpis: bool,
170    pub ces: bool,
171    pub ir: bool,
172    pub rwp: bool,
173    #[bits(20)]
174    _res_4_23: u32,
175    pub dpg0: bool,
176    pub dpg1ns: bool,
177    pub dpg1s: bool,
178    #[bits(4)]
179    _res_27_30: u32,
180    pub uwp: bool,
181}
182
183#[bitfield(u32)]
184pub struct GicrWaker {
185    /// Implementation defined.
186    pub bit_0: bool,
187    pub processor_sleep: bool,
188    pub children_asleep: bool,
189    #[bits(28)]
190    _res_3_30: u32,
191    /// Implementation defined.
192    pub bit_31: bool,
193}
194
195#[bitfield(u64)]
196pub struct GicrSgi {
197    pub target_list: u16,
198    pub aff1: u8,
199    #[bits(4)]
200    pub intid: u32,
201    #[bits(4)]
202    _res_28_31: u16,
203    pub aff2: u8,
204    pub irm: bool,
205    #[bits(3)]
206    _res_41_43: u8,
207    #[bits(4)]
208    pub rs: u8,
209    pub aff3: u8,
210    _res_56_63: u8,
211}
aarch64defs/gic.rs

aarch64defs/
gic.rs
