aarch64defs/
gic.rs

1// Copyright (c) Microsoft Corporation.
2// Licensed under the MIT License.
3
4//! Definitions for the Generic Interrupt Controller (GIC) registers.
5
6use bitfield_struct::bitfield;
7use core::ops::Range;
8use open_enum::open_enum;
9
10open_enum! {
11    /// Registers in an ARM GIC v2m MSI frame (ARM IHI 0048B).
12    pub enum GicV2mRegister: u16 {
13        /// MSI type register — contains SPI count and base.
14        TYPER       = 0x0008,
15        /// Write the GIC interrupt ID here to assert a non-secure SPI.
16        SETSPI_NS   = 0x0040,
17        /// Implementation identification register.
18        IIDR        = 0x0FCC,
19        /// Peripheral ID 2 register.
20        PIDR2       = 0x0FE8,
21    }
22}
23
24open_enum! {
25    pub enum GicdRegister: u16 {
26        CTLR = 0x0000,
27        TYPER = 0x0004,
28        IIDR = 0x0008,
29        TYPER2 = 0x000c,
30        STATUSR = 0x0010,
31        SETSPI_NSR = 0x0040,
32        CLRSPI_NSR = 0x0048,
33        SETSPI_SR = 0x0050,
34        CLRSPI_SR = 0x0058,
35        IGROUPR0 = 0x0080,       // 0x80
36        ISENABLER0 = 0x0100,     // 0x80
37        ICENABLER0 = 0x0180,     // 0x80
38        ISPENDR0 = 0x0200,       // 0x80
39        ICPENDR0 = 0x0280,       // 0x80
40        ISACTIVER0 = 0x0300,     // 0x80
41        ICACTIVER0 = 0x0380,     // 0x80
42        IPRIORITYR0 = 0x0400,    // 0x400
43        ITARGETSR0 = 0x0800,     // 0x400
44        ICFGR0 = 0x0c00,         // 0x100
45        IGRPMODR0 = 0x0d00,      // 0x100
46        NSACR0 = 0x0e00,         // 0x100
47        SGIR = 0x0f00,
48        CPENDSGIR0 = 0x0f10,     // 0x10
49        SPENDSGIR0 = 0x0f20,     // 0x10
50        INMIR0 = 0x0f80,         // 0x80
51        IROUTER0 = 0x6000,       // 0x2000, skip first 0x100,
52        PIDR2 = 0xffe8,
53    }
54}
55
56impl GicdRegister {
57    pub const IGROUPR: Range<u16> = Self::IGROUPR0.0..Self::IGROUPR0.0 + 0x80;
58    pub const ISENABLER: Range<u16> = Self::ISENABLER0.0..Self::ISENABLER0.0 + 0x80;
59    pub const ICENABLER: Range<u16> = Self::ICENABLER0.0..Self::ICENABLER0.0 + 0x80;
60    pub const ISPENDR: Range<u16> = Self::ISPENDR0.0..Self::ISPENDR0.0 + 0x80;
61    pub const ICPENDR: Range<u16> = Self::ICPENDR0.0..Self::ICPENDR0.0 + 0x80;
62    pub const ISACTIVER: Range<u16> = Self::ISACTIVER0.0..Self::ISACTIVER0.0 + 0x80;
63    pub const ICACTIVER: Range<u16> = Self::ICACTIVER0.0..Self::ICACTIVER0.0 + 0x80;
64    pub const ICFGR: Range<u16> = Self::ICFGR0.0..Self::ICFGR0.0 + 0x100;
65    pub const IPRIORITYR: Range<u16> = Self::IPRIORITYR0.0..Self::IPRIORITYR0.0 + 0x400;
66    pub const IROUTER: Range<u16> = Self::IROUTER0.0..Self::IROUTER0.0 + 0x2000;
67}
68
69#[bitfield(u32)]
70pub struct GicdTyper {
71    #[bits(5)]
72    pub it_lines_number: u8,
73    #[bits(3)]
74    pub cpu_number: u8,
75    pub espi: bool,
76    pub nmi: bool,
77    pub security_extn: bool,
78    #[bits(5)]
79    pub num_lpis: u8,
80    pub mbis: bool,
81    pub lpis: bool,
82    pub dvis: bool,
83    #[bits(5)]
84    pub id_bits: u8,
85    pub a3v: bool,
86    pub no1n: bool,
87    pub rss: bool,
88    #[bits(5)]
89    pub espi_range: u8,
90}
91
92#[bitfield(u32)]
93pub struct GicdTyper2 {
94    #[bits(5)]
95    pub vid: u8,
96    #[bits(2)]
97    _res5_6: u8,
98    pub vil: bool,
99    pub n_assgi_cap: bool,
100    #[bits(23)]
101    _res9_31: u32,
102}
103
104#[bitfield(u32)]
105pub struct GicdCtlr {
106    pub enable_grp0: bool,
107    pub enable_grp1: bool,
108    #[bits(2)]
109    _res_2_3: u8,
110    pub are: bool,
111    _res_5: bool,
112    pub ds: bool,
113    pub e1nwf: bool,
114    pub n_assgi_req: bool,
115    #[bits(22)]
116    _res_9_30: u32,
117    pub rwp: bool,
118}
119
120open_enum! {
121    pub enum GicrRdRegister: u16 {
122        CTLR = 0x0000,
123        IIDR = 0x0004,
124        TYPER = 0x0008,     // 64 bit
125        STATUSR = 0x0010,
126        WAKER = 0x0014,
127        MPAMIDR = 0x0018,
128        PARTIDR = 0x001c,
129        SETLPIR = 0x0040,   // 64 bit
130        CLRLPIR = 0x0048,   // 64 bit
131        PROPBASER = 0x0070, // 64 bit
132        PENDBASER = 0x0078, // 64 bit
133        INVLPIR = 0x00A0,   // 64 bit
134        SYNCR = 0x00C0,     // 64 bit
135        PIDR2 = 0xffe8,
136    }
137}
138
139open_enum! {
140    pub enum GicrSgiRegister: u16 {
141        IGROUPR0 = 0x0080,
142        ISENABLER0 = 0x0100,
143        ICENABLER0 = 0x0180,
144        ISPENDR0 = 0x0200,
145        ICPENDR0 = 0x0280,
146        ISACTIVER0 = 0x0300,
147        ICACTIVER0 = 0x0380,
148        IPRIORITYR0 = 0x0400, // 0x20
149        ICFGR0 = 0x0c00,
150        ICFGR1 = 0x0c04,
151        IGRPMODR0 = 0x0d00,
152    }
153}
154
155impl GicrSgiRegister {
156    pub const IPRIORITYR: Range<u16> = Self::IPRIORITYR0.0..Self::IPRIORITYR0.0 + 0x20;
157}
158
159#[bitfield(u64)]
160pub struct GicrTyper {
161    pub plpis: bool,
162    pub vlpis: bool,
163    pub dirty: bool,
164    pub direct_lpi: bool,
165    pub last: bool,
166    pub dpgs: bool,
167    pub mpam: bool,
168    pub rvpeid: bool,
169    pub processor_number: u16,
170    #[bits(2)]
171    pub common_lpi_aff: u8,
172    pub vsgi: bool,
173    #[bits(5)]
174    pub ppi_num: u8,
175    pub aff0: u8,
176    pub aff1: u8,
177    pub aff2: u8,
178    pub aff3: u8,
179}
180
181#[bitfield(u32)]
182pub struct GicrCtlr {
183    pub enable_lpis: bool,
184    pub ces: bool,
185    pub ir: bool,
186    pub rwp: bool,
187    #[bits(20)]
188    _res_4_23: u32,
189    pub dpg0: bool,
190    pub dpg1ns: bool,
191    pub dpg1s: bool,
192    #[bits(4)]
193    _res_27_30: u32,
194    pub uwp: bool,
195}
196
197#[bitfield(u32)]
198pub struct GicrWaker {
199    /// Implementation defined.
200    pub bit_0: bool,
201    pub processor_sleep: bool,
202    pub children_asleep: bool,
203    #[bits(28)]
204    _res_3_30: u32,
205    /// Implementation defined.
206    pub bit_31: bool,
207}
208
209#[bitfield(u64)]
210pub struct GicrSgi {
211    pub target_list: u16,
212    pub aff1: u8,
213    #[bits(4)]
214    pub intid: u32,
215    #[bits(4)]
216    _res_28_31: u16,
217    pub aff2: u8,
218    pub irm: bool,
219    #[bits(3)]
220    _res_41_43: u8,
221    #[bits(4)]
222    pub rs: u8,
223    pub aff3: u8,
224    _res_56_63: u8,
225}
aarch64defs/gic.rs

aarch64defs/
gic.rs
