pub(super) fn cache_lines_flush_page(addr: u64)Expand description
Flush all cache lines covering a single page-sized region starting at the given virtual address.
On AMD SEV-SNP, the C-bit is part of the cache-line tag for a physical address. When transitioning a page between shared (C=0) and private (C=1) state, any cache lines tagged with the old C-bit setting must be evicted before the new mapping is accessed; otherwise stale cache lines can lead to data corruption observed via the new mapping. Callers must invoke this using a VA whose PTE has the C-bit setting that is being torn down.