Module invalidation 

Invalidation queue descriptor types for the Intel VT-d IOMMU.

Based on Intel VT-d Specification Rev 4.1, §§6.5.2 and 11.4.9. Queue entries are 128 or 256 bits. Type is the concatenation of bits 11:9 and 3:0, not just the low nibble. Legacy descriptors in a 256-bit queue have zero upper padding.

Structs

ContextCacheInvalidateDw0Dw1

Context-Cache Invalidation Descriptor (type 0x01, §6.5.2.1).

DescriptorType

Invalidation descriptor types (§6.5).

InterruptCacheInvalidateDw0Dw1

Interrupt Entry Cache Invalidation Descriptor (type 0x04, §6.5.2.7).

InvalidationDescriptor

A raw 128-bit invalidation queue descriptor (16 bytes).

InvalidationDescriptor256

A 256-bit descriptor, including the reserved upper half (§6.5.2).

InvalidationWaitDw0Dw1

Invalidation Wait Descriptor (type 0x05, §6.5.2.8).

InvalidationWaitDw2Dw3

Invalidation Wait Descriptor — high 64 bits.

IotlbInvalidateAddress

Address fields shared by IOTLB and P_IOTLB invalidations (§§6.5.2.3-.4).

IotlbInvalidateDw0Dw1

IOTLB Invalidation Descriptor (type 0x02, §6.5.2.3).

PasidInvalidateDw0Dw1

Common low word of PASID-cache and P_IOTLB descriptors (§§6.5.2.2, 6.5.2.4).

Enums

DescriptorWidth

Width of an entry, distinct from IQH/IQT’s fixed 16-byte register units.

Functions

parse_interrupt_cache_invalidate

Parse an InvalidationDescriptor as INTERRUPT_ENTRY_CACHE_INVALIDATE fields.

parse_invalidation_wait

Parse a InvalidationDescriptor as INVALIDATION_WAIT fields.